W83627SF-AW Winbond, W83627SF-AW Datasheet - Page 29

• Manufacturer Part Number: W83627SF-AW
• Manufacturer: Winbond

Specifications of W83627SF-AW

• Pin Count: 128
• Lead Free Status / RoHS Status: Not Compliant

Bit 6: TSRE. If the transmitting FIFO and TSR are both empty, it will be set to a logical 1. Otherwise,
Bit 5: TBRE. When a data character is transferred from TBR to TSR, this bit will be set to a logical 1.
Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full
Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. When
Bit 2: PBER. This bit is set to a logical 1 to indicate that parity bit of received data is incorrect. When
Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next
Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by CPU in the
5.9
This 8-bit register provides control settings for Smart Card interface.
Bit 7 – 6: These two bits (BASESEL1 and BASESEL0 respectively) select internal sampling clock
Bit 5 – 4: These two bits (CLKSEL1 and CLKSEL0 respectively) select frequency of SCCLK.
this bit will be reset to a logical 0.
If ETBREI of ICR is a logical 1, an interrupt will be generated to notify the CPU to write the next
data. It will be reset to a logical 0 when CPU writes data into TBR or FIFO.
word time, including start bit, data bits, parity bit, and stop bits. When the CPU reads SCSR, it
will clear this bit to a logical 0.
CPU reads SCSR, it will clear this bit to a logical 0.
CPU reads SCSR, it will clear this bit to a logical 0.
received data before they were read by CPU. When CPU reads USR, it will clear this bit to a
logical 0.
RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0.
Extended Control Register (ECR, at "base address + 7")
base multiplier versus baud rate.
7
6
BASESEL1, BASESEL0
5
4
00
01
10
11
3
2
1
0
- 29 -
Warm reset
SCIO direction
CLKSTP
CLKSTPH
SCCLK frequency select bit 0
SCCLK frequency select bit 1
Internal sampling clock base select bit 0
Internal sampling clock base select bit 1
Publication Release Date: May 31, 2005
MULTIPLIER
14x
16x
18x
16x
W83627SF
Revision A1