W83627SF-AW Winbond, W83627SF-AW Datasheet - Page 33

• Manufacturer Part Number: W83627SF-AW
• Manufacturer: Winbond

Specifications of W83627SF-AW

• Pin Count: 128
• Lead Free Status / RoHS Status: Not Compliant

TABLE 6-1 UART Register Bit Map , continued
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit
Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT will
Bit 2: MSBE. This bit defines the number of stop bits in each serial character that is transmitted or
(1) If MSBE is set to a logical 0, one stop bit is sent and checked.
(2) If MSBE is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and
(3) If MSBE is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and checked.
Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in
BDLAB = 1
BDLAB = 1
Register Address Base
+ 3
+ 4
+ 5
+ 6
+ 7
+ 0
+ 1
3 is programmed. When this bit is set, an even number of logic 1's are sent or checked. When
the bit is reset, an odd number of logic 1's are sent or checked.
be stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same
position as the transmitter will be detected.
received.
checked.
each serial character.
UART Control
UART Status
User Defined
Divisor Latch
Divisor Latch
Handshake
Handshake
Baudrate
Register
Register
Register
Register
Register
Baudrate
Control
Status
High
Low
UCR
HCR
UDR
USR
HSR
BHL
BLL
RBR Data
Terminal
Toggling
(TCTS)
(DLS0)
Length
Ready
Ready
(RDR)
Select
(DTR)
Data
Bit 0
Data
CTS
Bit 0
Bit 0
Bit 8
0
Toggling
Request
Overrun
(TDSR)
(DLS1)
Length
(OER)
Select
(RTS)
Send
Error
Data
Bit 1
DSR
Bit 1
Bit 1
Bit 9
to
1
Loopback
RI Falling
Stop Bits
Parity Bit
(MSBE)
Multiple
(PBER)
Enable
BIT NUMBER
(FERI)
Bit 10
Edge
- 33 -
Input
Error
Bit 2
Bit 2
RI
2
Toggling
No Stop
(NSER)
(TDCD)
Enable
Enable
Parity
(PBE)
Bit 11
Error
DCD
Bit 3
Bit 3
IRQ
Bit
Bit
3
Publication Release Date: May 31, 2005
Loopback
Detected
to Send
Internal
Enable
Enable
(SBD)
Parity
(EPE)
(CTS)
Bit 12
Silent
Even
Clear
Bit 4
Bit 4
Byte
4
Bit Fixed
Data Set
(TBRE)
Enable
PBFE)
Empty
Ready
(DSR)
Parity
Bit 13
TBR
Bit 5
Bit 5
5
0
W83627SF
Indicator
Silence
(TSRE)
Enable
Empty
(SSE)
Bit 14
TSR
Ring
Bit 6
Bit 6
(RI)
Set
6
0
Revision A1
Indication
Baudrate
(BDLAB)
RX FIFO
(RFEI) **
Access
Divisor
Carrier
Detect
(DCD)
Bit 15
Latch
Error
Data
Bit 7
Bit 7
Bit
7
0