NH82801DBSL8DE 869490 Intel, NH82801DBSL8DE 869490 Datasheet - Page 156
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NH82801DBSL8DE 869490
Manufacturer Part Number
NH82801DBSL8DE 869490
Description
Manufacturer
Intel
Datasheet
1.NH82801DBSL8DE_869490.pdf
(587 pages)
Specifications of NH82801DBSL8DE 869490
Lead Free Status / RoHS Status
Compliant
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Functional Description
156
The following rules/steps apply if the system is in a G0 state and the policy is for the ICH4 to
reboot the system after a hardware lockup:
The following rules/steps apply if the system is in a G0 state and the policy is for the ICH4 to not
reboot the system after a hardware lockup.
10. After step 8 (reset attempt), if the reset is unsuccessful, then the ICH4 continues sending a
1. Upon detecting the lockup the SECOND_TO_STS bit will be set. The ICH4 may send up to 1
2. If the reboot at step 1 is successful, BIOS should clear the SECOND_TO_STS bit. This
3. If the reboot attempt in step 1 is not successful, then the timer will timeout a third time. At this
4. After step 3 (unsuccessful reboot after third timeout), if the user does a Power Button
5. After step 4 (power button override after unsuccessful reboot) if the user presses the Power
6. If step 5 (power button press) is successful in waking the system, the ICH4 continues sending
7. If step 5 (power button press) is unsuccessful in waking the system, the ICH4 continues
8. After step 3 (unsuccessful reboot after third timeout), if a reset is attempted (using a button
9. After step 8 (reset attempt) if the reset is successful, BIOS is run. The ICH4 continues sending
1. Upon detecting the lockup the SECOND_TO_STS bit is set. The ICH4 sends a message with
2. After step 1, the ICH4 sends a message every heartbeat period until some external intervention
3. Rules/steps 4–10 apply if no user intervention (resets, power button presses, SMBus reset
4. After step 3 (third timeout), if the user does a Power Button Override, the system goes to an S5
Event message to the D110. The ICH4 then attempts to reboot the processor.
prevents any further Heartbeats from being sent. The BIOS may then perform addition
recovery/boot steps. (See note 2.)
point the system has locked up and was unsuccessful in rebooting. The ICH4 does not attempt
to automatically reboot again. The ICH4 starts sending a message every heartbeat period
(30–32 seconds). The heartbeats continue until some external intervention occurs (reset, power
failure, etc.).
Override, the system goes to an S5 state. The ICH4 continues sending the messages every
heartbeat period.
Button again, the system should wake to an S0 state and the processor should start executing
the BIOS.
messages every heartbeat period until the BIOS clears the SECOND_TO_STS bit. (See note 2)
sending a message every heartbeat period. The ICH4 does not attempt to automatically reboot
again. The ICH4 will start sending a message every heartbeat period (30–32 seconds). The
heartbeats continue until some external intervention occurs (reset, power failure, etc.).
(See note 3)
that pulses PWROK low or via the message on the SMBus slave interface), the ICH4 attempts
to reset the system.
a message every heartbeat period until the BIOS clears the SECOND_TO_STS bit.
(See note 2)
message every heartbeat period. The ICH4 does not attempt to reboot the system again without
external intervention. (See note 3)
the Watchdog (WD) Event status bit set (and any other bits that must also be set). This
message is sent as soon as the lockup is detected, and is sent with the next (incremented)
sequence number.
occurs.
messages) occur after a third timeout of the watchdog timer. If the intervention occurs before
the third timeout, then jump to rule/step11.
state. The ICH4 continues sending heartbeats at this point.
Intel
®
82801DB ICH4 Datasheet
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