NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 83

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

4.3.2.
Datasheet
Table 12. Data Bytes on DIMM Used for Programming DRAM Registers
R
DRAM Address Translation and Decoding
Table 12 is only a subset of the defined SPD bytes on the DIMM module. These bytes collectively
provide enough data for BIOS to program the GMCH DRAM registers.
The GMCH contains address decoders that translate the address received on the host bus, hub interface,
or from the internal Graphics device to an effective memory address. The GMCH supports 16 and 64
Mbit SDRAM devices. The GMCH supports a 2 KB page sizes only. The multiplexed row / column
address to the DRAM memory array is provided by the SBS[1:0] and SMAA[11:0] signals and copies.
These addresses are derived from the host address bus as defined by by the following table for SDRAM
devices.
Row size is internally computed using the values programmed in the DRP register.
Up to 4 pages can be open at any time within any row (Only 2 active pages are supported in rows
populated with either 8 MBs or 16 MBs ).
36-41
Byte
12
17
42
2
3
4
5
Memory Type (EDO, SDRAM) the GMCH only supports SDRAM.
# of Row Addresses, not counting Bank Addresses
# of Column Addresses
# of banks of DRAM (Single or Double sided) DIMM
Refresh Rate
# Banks on each SDRAM Device
Access Time from Clock for CAS# Latency 1 through 7
Data Width of SDRAM Components
Function
Intel
®
82810E (GMCH)
83