RG82852GME S L72K Intel, RG82852GME S L72K Datasheet

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RG82852GME S L72K

Manufacturer Part Number
RG82852GME S L72K
Description
Manufacturer
Intel
Datasheet

Specifications of RG82852GME S L72K

Lead Free Status / RoHS Status
Not Compliant
Intel
Graphics and Memory Controller
Hub (GMCH)
Specification Update
November 2004
R
Notice: The Intel
as errata, which may cause the product to deviate from published specifications. Current
characterized errata are documented in this Specification Update.
852GME / 852PM Chipset
852GME/852PM chipset may contain design defects or errors known
Document Number: 253562-003

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RG82852GME S L72K Summary of contents

Page 1

... Graphics and Memory Controller Hub (GMCH) Specification Update November 2004  Notice: The Intel 852GME/852PM chipset may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update. Document Number: 253562-003 ...

Page 2

... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com. ...

Page 3

... Contents Revision History .................................................................................................................. 5 Preface ................................................................................................................................ 6 Summary Table of Changes ............................................................................................... 8 Errata................................................................................................................................. 10 Specification Changes ...................................................................................................... 13 Specification Clarifications ................................................................................................ 14 Documentation Changes .................................................................................................. 15 4 ® Intel 852GME/852PM Specification Update R ...

Page 4

... R Revision History Revision - 001 Initial Release - 002 Added specification update on support for Mobile Intel with Hyper-Threading Technology. • - 003 Added Errata A7/B7 • Added Specification Change #2 • Added Documentation Changes #1 & 2 ® Intel 852GME/852PM Specification Update Description ® ® Pentium 4 Processors § ...

Page 5

... Specification Changes are modifications to the current published specifications. These changes will be incorporated in the next release of the specifications. Errata are design defects or errors. Errata may cause the Intel® 852GME/852PM Chipset GMCH/MCH behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices ...

Page 6

... R Component Identification via Programming Interface The Intel 852GME and Intel 852PM chipset GMCH/MCH may be identified by the following register contents. Stepping A2 NOTES: 1. The Vendor ID corresponds to bits 15-0 of the Vendor ID Register located at offset 00-01h in the PCI function 0 configuration space. 2. The Device ID corresponds to bits 15-0 of the Device ID Register located at offset 02-03h in the PCI function 0 configuration space ...

Page 7

... The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes that apply to the listed Intel 852GME/852PM chipset GMCH/MCH steppings. Intel intends to fix some of the errata in a future stepping of the component and to account for the other outstanding issues through documentation or Specification Changes as noted. This table uses the ...

Page 8

... No Fix Anomalous System Behavior May Occur When AGP GART Size Is 64MB and APBASE bit 27 Is Set PLANS SPECIFICATION CHANGES Added support for Mobile Intel® Pentium® 4 Processors with Hyper-Threading Technology. 24-Bit LVDS Will Not Be Supported On 852GME Platforms PLANS SPECIFICATION CLARIFICATIONS ...

Page 9

... Based on the lack of customer or end user reported issues related to this erratum, the number of VGA applications that run in 40-column modes and also use non-black border colors is low. Based on Intel’s validation and compatibility testing, the number of CRT monitors that exhibit this color anomaly is also low. ...

Page 10

... Note that upstream AGP FRAME#-based PCI writes which cross a 32-byte aligned boundary are expected to be rare. Implication: The issue may cause display corruption or a system hang. With the workaround implemented, Intel has done extensive validation and expects less than 3% impact on system performance. ...

Page 11

... Implication: Problem may result in anomalous system behavior which can cause a system hang. Workaround: Use an aperture base size of 128MB or 256MB. If using a 64MB aperture size, set APBASE such that bit 27 is cleared (e.g. use 0xD0000000 instead of 0xD8000000). Status: There are no plans to fix this erratum in silicon. 12 § ® Intel 852GME/852PM Specification Update R ...

Page 12

... R Specification Changes ® 1. Mobile Intel Pentium supported by the Intel The following text should be added to the section titled “Intel 852PM Chipset MCH Features” under bullet “Processor/Host Bus Support” (p 12). ® - Mobile Intel Pentium 2. 24-bit LVDS will not be supported on 852GME platforms Due to no availability of 24-Bit LVDS panels for validation, 24-Bit LVDS support is dropped from 852GME platforms ...

Page 13

... Specification Clarifications Strapping Option Clarification 1. Notes 1, 2, and 3 have been added to Table 53, “Strapping Configuration Table” in Section 7.1, pg 227 of the 852GME/852PM datasheet. GST[2] §Clock Config: Bit_2 Note: Intel PSB 400 = 0 852GME PSB 533 = 1 GMCH Only NOTES: 1. External pull-ups/downs will be required on the board to enable the non-default state of the straps. ...

Page 14

... D28. Actual ball definition is AD28. D28 is a VSS ball. This is the only reference where RSTIN# is incorrectly defined. Ballout and Package Information in Section 8 are correct. Sections 6.3 and 8 incorrectly show some signal pins as reserved 2. Section 6.3 Table 50 and Section 8 Table 55 show balls D2, D3, B3, F2, F3 & reserved. Balls should be defined as follows for Intel Ball Signal Name D2 GWBF# ...

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