LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 66

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

Bit 1
This bit enables the Transmitter Holding Register Empty Interrupt when set to logic “1”.
Bit 2
This bit enables the Received Line Status Interrupt when set to logic “1”. The error sources causing the interrupt are
Overrun, Parity, Framing and Break. The Line Status Register must be read to determine the source.
Bit 3
This bit enables the MODEM Status Interrupt when set to logic “1”. This is caused when one of the Modem Status
Register bits changes state.
Bits 4 through 7
These bits are always logic “0”.
FIFO CONTROL REGISTER (FCR)
Address Offset = 2H, DLAB = X, WRITE
This is a write only register at the same location as the IIR. This register is used to enable and clear the FIFOs, set
the RCVR FIFO trigger level. Note: DMA is not supported. The UART1 and UART2 FCR’s are shadowed in the
UART1 FIFO Control Shadow Register (runtime register at offset 0x20) and UART2 FIFO Control Shadow Register
(runtime register at offset 0x21).
Bit 0
Setting this bit to a logic “1” enables both the XMIT and RCVR FIFOs. Clearing this bit to a logic “0” disables both
the XMIT and RCVR FIFOs and clears all bytes from both FIFOs. When changing from FIFO Mode to non-FIFO
(16450) mode, data is automatically cleared from the FIFOs. This bit must be a 1 when other bits in this register are
written to or they will not be properly programmed.
Bit 1
Setting this bit to a logic “1” clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is
not cleared. This bit is self-clearing.
Bit 2
Setting this bit to a logic “1” clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift register is not
cleared. This bit is self-clearing.
Bit 3
Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this
chip.
Bit 4,5
Reserved
Bit 6,7
These bits are used to set the trigger level for the RCVR FIFO interrupt.
INTERRUPT IDENTIFICATION REGISTER (IIR)
Address Offset = 2H, DLAB = X, READ
By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four levels of
priority interrupt exist. They are in descending order of priority:
1.
2.
3.
4.
SMSC DS – LPC47M192
Receiver Line Status (highest priority)
Received Data Ready
Transmitter Holding Register Empty
MODEM Status (lowest priority)
DATASHEET
Page 66
Rev. 03/30/05