LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet - Page 83

• Manufacturer Part Number: LPC47M192-NW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M192-NW

• Lead Free Status / RoHS Status: Compliant

7.7.7.1
When the Activate bit D0 is ‘0’, the MPU-401 I/O base address decoder is disabled, the IRQ is always deasserted,
and the MPU-401 hardware is in a minimum power-consumption state. When the Activate bit is ‘1’, the MPU-401 I/O
base address decoder and the IRQ are enabled, and the MPU-401 hardware is fully powered.
Register 0x60 is the MPU-401 I/O Base Address High Byte, register 0x61 is the MPU-401 I/O Base Address Low
Byte. The MPU-401 I/O base address is programmable on even-byte boundaries. The valid MPU-401 I/O base
address range is 0x0100 – 0x0FFE. See Section “Host Interface”.
7.8 PARALLEL PORT
The LPC47M192 incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-
directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel
port modes. Refer to the Configuration Registers for information on disabling, power down, changing the base
address of the parallel port, and selecting the mode of operation.
The parallel port also incorporates SMSC’s ChiProtect circuitry, which prevents possible damage to the parallel port
due to printer power-up.
The functionality of the Parallel Port is achieved through the use of eight addressable ports, with their associated
registers and control gating. The control and data port are read/write by the CPU, the status port is read/write in the
EPP mode. The address map of the Parallel Port is shown below:
The bit map of these registers is:
SMSC DS – LPC47M192
DATA PORT
STATUS PORT
CONTROL PORT
EPP ADDR PORT
Note 1: These registers are available in all modes.
Note 2: These registers are only available in EPP mode.
DATA PORT
STATUS
PORT
CONTROL
PORT
EPP ADDR
PORT
EPP DATA
PORT 0
EPP DATA
PORT 1
EPP DATA
PORT 2
EPP DATA
PORT 3
CONNECTOR
Activate and I/O Base address
HOST
2-9
10
11
1
STROBE AUTOFD
TMOUT
PD0
PD0
PD0
PD0
PD0
PD0
D0
BASE ADDRESS + 00H
BASE ADDRESS + 01H
BASE ADDRESS + 02H
BASE ADDRESS + 03H
PIN NUMBER
68-75
83
80
79
PD1
PD1
PD1
PD1
PD1
PD1
D1
0
Table 39 - Parallel Port Connector
DATASHEET
nINIT
nSTROBE
PD<0:7>
nACK
BUSY
PD2
PD2
PD2
PD2
PD2
PD2
D2
0
STANDARD
nERR
Page 83
PD3
SLC
PD3
PD3
PD3
PD3
PD3
D3
SLCT
IRQE
PD4
PD4
PD4
PD4
PD4
PD4
D4
nWrite
PData<0:7>
Intr
nWait
EPP DATA PORT 0
EPP DATA PORT 1
EPP DATA PORT 2
EPP DATA PORT 3
EPP
PCD
PD5
PD5
PD5
PD5
PD5
PD5
PE
D5
nACK
PD6
PD6
PD6
PD6
PD6
PD6
D6
0
nStrobe
PData<0:7>
nAck
Busy, PeriphAck(3)
BASE ADDRESS + 04H
BASE ADDRESS + 05H
BASE ADDRESS + 06H
BASE ADDRESS + 07H
nBUSY
PD7
PD7
PD7
PD7
PD7
PD7
D7
ECP
0
Note
1
1
1
2
2
2
2
2
Rev. 03/30/05