ISP1161A1BMGA STEricsson, ISP1161A1BMGA Datasheet - Page 23
ISP1161A1BMGA
Manufacturer Part Number
ISP1161A1BMGA
Description
Manufacturer
STEricsson
Datasheet
1.ISP1161A1BMGA.pdf
(137 pages)
Specifications of ISP1161A1BMGA
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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ISP1161A1_5
Product data sheet
Event A (see
bit INTENA set to logic 0, an interrupt will not be generated at pin INT2. However, it will be
registered in the corresponding DcInterrupt register bit.
Event B (see
bit SOF in the DcInterrupt register is already asserted.
Event C (see
asserted. The bold dashed line shows the desired behavior of pin INT2.
De-assertion of pin INT2 can be achieved in the following manner. Bits[23:8] of the
DcInterrupt register are endpoint interrupts. These interrupts are cleared on reading their
respective DcEndpointStatus register. Bits[7:0] of the DcInterrupt register are bus status
and EOT interrupts that are cleared on reading the DcInterrupt register. Make sure that
bit INTENA is set to logic 1 when you perform the clear interrupt commands.
For more information on interrupt control, see
Section
13.3.6.
Figure
Figure
Figure
22): When an interrupt event occurs (for example, SOF interrupt) with
22): When bit INTENA is set to logic 1, pin INT2 is asserted because
22): If the firmware sets bit INTENA to logic 0, pin INT2 will still be
Rev. 05 — 29 September 2009
USB single-chip host and device controller
Section
13.1.3,
Section 13.1.5
ISP1161A1
© ST-ERICSSON 2009. All rights reserved.
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