CY7C63231A-PC Cypress Semiconductor Corp, CY7C63231A-PC Datasheet - Page 41

• Manufacturer Part Number: CY7C63231A-PC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C63231A-PC

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Not Compliant

21.0
Document #: 38-08028 Rev. *B
Address
0x0A
0x0B
0x0C
0x0D
0xF8
0x11,
0x1F
0xFF
0x00
0x01
0x02
0x04
0x05
0x06
0x07
0x10
0x12
0x14
0x13
0x20
0x21
0x24
0x25
Register Summary
Port 0 Data
Port 1 Data
Port 2 Data
GPIO Port 0 Mode 0
GPIO Port 0 Mode 1
GPIO Port 1 Mode 0
GPIO Port 1 Mode 1
Port 0 Interrupt Enable
Port 1 Interrupt Enable
Port 0 Interrupt Polarity
Port 1 Interrupt Polarity
Clock Configuration
USB Device Address
EP0 Mode
EP1 Mode Register
EP0 and 1Counter
USB Status and Control
Global Interrupt Enable
Endpoint Interrupt Enable
Timer LSB
Timer (MSB)
Process Status & Control
Register Name
Ext. Clock
PS/2 Pull-
Received
Wake-up
Resume
Data 0/1
Interrupt
Address
Pending
SETUP
Device
Enable
Enable
Enable
STALL
Toggle
Delay
Bit 7
IRQ
up
Reserved
FOR
FOR
Watch Dog
Data Valid
Received
Interrupt
Enable
Enable
VREG
GPIO
Reset
Bit 6
IN
Wake-up Timer Adjust Bit [2:0]
Reserved
Reserved
USB Reset-
D+(SCLK)
Received
Interrupt
Interrupt
Activity
Mode
Event
State
Bit 5
OUT
PS/2
Bus
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
D- (SDATA)
Transaction
Transaction
P0[7:0] Interrupt Polarity
P0[7:0] Interrupt Enable
Reserved
Reserved
LVR/BOR
ACKed
ACKed
Reset
State
Bit 4
P0[7:0] Mode0
P0[7:0] Mode1
Timer Bit [7:0]
P0
Device Address
Low Voltage
Reserved
USB Bus
Suspend
Disable
Activity
Reset
Bit 3
P2.2(Int Clk
Mode only)
Precision
1.024 ms
Clocking
Interrupt
Interrupt
Enable
Enable
Enable
Sense
Bit 2
USB
Timer Bit [11:8]
Byte Count
Mode Bit
Mode Bit
D+/D- Forcing Bit
P2.1 (Int Clk
Mode only)
P1[1:0] Interrupt Polarity
P1[1:0] Interrupt Enable
Reserved
Interrupt
Interrupt
Internal
Disable
Output
Enable
Enable
128 µs
Clock
Bit 1
EP1
P1[1:0] Mode0
P1[1:0] Mode1
CY7C63221/31A
P1[1:0]
enCoRe™ USB
Reset-PS/2
Activity Intr.
P2.0 Vreg
Oscillator
USB Bus
Pin State
External
Interrupt
Enable
Enable
Enable
Bit 0
EP0
Run
WWWWWWWW
WWWWWWWW
WWWWWWWW
WWWWWWWW
Read/Write)/
RRRRRRRR
BBBBBBBB
BBBBBBBB
BBBBBBBB
BBBBBBBB
BBB
RBBBBR
--
B
BB
Both(B)
BB
----
------
------
------
------
------
------
--
RR
--
BBBBB
---
RRRR
-
BBBB
-
BBBB
Page 41 of 50
RRR
WW
WW
WW
WW
BBB
BB
BB
-
B
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
Default/
Section
Reset
See
18.0
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