LE3100MICH S L8YC Intel, LE3100MICH S L8YC Datasheet - Page 74

• Manufacturer Part Number: LE3100MICH S L8YC
• Manufacturer: Intel

Specifications of LE3100MICH S L8YC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Table 4-3.
74
Signal Description (Sheet 5 of 8)
INIT#
ITP_CLK[1:0]
LINT[1:0]
LOCK#
MSID[1:0]
PECI
PROCHOT#
PSI#
PWRGOOD
Name
Output
Output
Output
Output
Output
Input/
Input/
Input/
Type
Input
Input
Input
Input
processor without affecting its internal caches or floating-point registers. The
processor then begins execution at the power-on Reset vector configured
during power-on configuration. The processor continues to handle snoop
requests during INIT# assertion. INIT# is an asynchronous signal and must
connect the appropriate pins/lands of all processor FSB agents.
If INIT# is sampled active on the active to inactive transition of RESET#,
then the processor executes its Built-in Self-Test (BIST).
where no debug port is implemented on the system board. ITP_CLK[1:0] are
used as BCLK[1:0] references for a debug port implemented on an
interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are
no connects in the system. These are not processor signals.
all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes
INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a
nonmaskable interrupt. INTR and NMI are backward compatible with the
signals of those names on the Pentium processor. Both signals are
asynchronous.
Both of these signals must be software configured via BIOS programming of
the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because
the APIC is enabled by default after Reset, operation of these signals as
LINT[1:0] is the default configuration.
LOCK# indicates to the system that a transaction must occur atomically. This
signal must connect the appropriate pins/lands of all processor FSB agents.
For a locked sequence of transactions, LOCK# is asserted from the beginning
of the first transaction to the end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the
processor FSB, it will wait until it observes LOCK# de-asserted. This enables
symmetric agents to retain ownership of the processor FSB throughout the
bus locked operation and ensure the atomicity of lock.
alternative to MSID, Intel has implemented the Power Segment Identifier
(PSID) to report the maximum Thermal Design Power of the processor. Refer
to the Platform Design Guide for additional information regarding PSID.
PECI is a proprietary one-wire bus interface. See
As an output, PROCHOT# (Processor Hot) will go active when the processor
temperature monitoring sensor detects that the processor has reached its
maximum safe operating temperature. This indicates that the processor
Thermal Control Circuit (TCC) has been activated, if enabled. As an input,
assertion of PROCHOT# by the system will activate the TCC, if enabled. The
TCC will remain active until the system de-asserts PROCHOT#. See
Section 5.2.4
Processor Power Status Indicator Signal. This signal may be asserted when
the processor is in the Deeper Sleep State. PSI# can be used to improve load
efficiency of the voltage regulator, resulting in platfrom power savings. Refer
to the Voltage Regulator-Down (VRD) 11.1 Processor Power Delivery Design
Guidelines for details on the PSI# signal.
PWRGOOD (Power Good) is a processor input. The processor requires this
signal to be a clean indication that the clocks and power supplies are stable
and within their specifications. ‘Clean’ implies that the signal will remain low
(capable of sinking leakage current), without glitches, from the time that the
power supplies are turned on until they come within specification. The signal
must then transition monotonically to a high state. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable before a
subsequent rising edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
INIT# (Initialization), when asserted, resets integer registers inside the
ITP_CLK[1:0] are copies of BCLK that are used only in processor systems
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins/lands of
On a processor these signals are connected on the package to Vss. As an
for more details.
Description
Land Listing and Signal Descriptions
Chapter 5.3
for details.
Datasheet