LSI53C1000R LSI, LSI53C1000R Datasheet
LSI53C1000R
Specifications of LSI53C1000R
Available stocks
Related parts for LSI53C1000R
LSI53C1000R Summary of contents
Page 1
... Ultra320 SCSI and to PCI-X. Because the LSI53C1000R is packaged in the same BGA as the LSI53C1020 PCI-X to Single Channel Ultra320 SCSI Controller, a motherboard can be designed now to accept either part without the need for redesign. The LSI53C1000R is identical in function to the proven LSI53C1000 PCI-Single Channel Ultra160 SCSI Controller. ...
Page 2
... SureLINK domain validation technology detects the configuration of the SCSI bus and automatically tests and adjusts the SCSI transfer rate to optimize interoperability. The LSI53C1000R exceeds Ultra160 by providing not only Basic (Level 1) and Enhanced (Level 2) domain validation, but adds Margined (Level 3) domain validation. This enhancement margins LVD drive strength and clock signal timing characteristics to identify marginal Ultra160 systems ...
Page 3
... Memory Interface MAD7-0 Figure 2. LSI53C1000R functional signal grouping The LSI53C1000R supports external expansion ROM through a parallel interface, for add-in card designs. For ease of software development and field upgrades of the ROM, the interface supports local programming of FLASH memory. A serial 2-wire interface provides a connection to an external serial EEPROM for storing Subsystem Vendor ID and Subsystem ID ...
Page 4
... The cable plant margining capability, exclusive to LSI Logic’s Ultra160 solution, includes end-to-end margining from the LSI53C1000R through LSI Logic’s LSI53C180 SCSI bus expander to the target device. The domain validation capability of SDMS software is available as an independent application as well as integrated in the DMI 2 ...