LH79525N0Q100A1 Sharp Electronics, LH79525N0Q100A1 Datasheet
LH79525N0Q100A1
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LH79525N0Q100A1 Summary of contents
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Product data sheet FEATURES • Highly Integrated System-on-Chip • High Performance: 76.205 MHz CPU Speed, 50.803 MHz maximum AHB clock (HCLK) • 32-bit ARM720T™ RISC Core – LH79524: 32-bit External Data Bus – 208 LFBGA package – LH79525: 16-bit External ...
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... LH79524/LH79525 ORDERING INFORMATION Type number Name LH79524N0F100A0 LFBGA208 LH79524N0F100A1 LFBGA208 LH79525N0Q100A0 LQFP176 LH79525N0Q100A1 LQFP176 2 NXP Semiconductors Table 1. Ordering information Package Description plastic low profile fine-pitch ball grid array pack- age; 208 balls plastic low profile fine-pitch ball grid array pack- age; 208 balls plastic low profile quad flat package ...
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System-on-Chip ARM720T CACHE INTERNAL INTERRUPTS INTERNAL 16KB SRAM BOOT ROM EXTERNAL MEMORY CONTROLLER USB DEVICE TEST SUPPORT LINEAR REGULATOR ADVANCED HIGH PERFORMANCE BUS (AHB) Figure 1. LH79524/LH79525 block diagram Product data sheet NXP Semiconductors MHz 32.768 kHz ...
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LH79524/LH79525 Figure 2. LH79524 pin configuration (LFBGA208) Figure 3. LH79525 pin configuration (LQFP176) 4 NXP Semiconductors LH79524 ball A1 index area ...
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System-on-Chip SIGNAL DESCRIPTIONS LFBGA SIGNAL NAME TYPE PIN T12 A0 R11 A1 T11 A2 P10 A3 R10 A4 T10 A10 P8 A11 T7 A12 R7 A13 P7 A14 T6 A15 ...
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LH79524/LH79525 Table 2. LH79524 Pin Descriptions (Cont’d) LFBGA SIGNAL NAME TYPE PIN K14 nOE J16 nWE A16 USBDN A15 USBDP E2 AN0/UL/X+ F2 AN1/UR/X– G2 AN2/LL/Y+/PJ3 H2 AN3/LR/Y–/PJ0 H3 AN4/WIPER/PJ1 F1 AN5/PJ5/INT5 F3 AN6/PJ7/INT7 E1 AN7/PJ6/INT6 G3 AN8/PJ4 G1 AN9/PJ2 ...
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System-on-Chip Table 2. LH79524 Pin Descriptions (Cont’d) LFBGA SIGNAL NAME TYPE PIN PB7/INT1/UARTTX0/ M3 UARTIRTX0 N7 PC0/A16 R6 PC1/A17 T5 PC2/A18 P6 PC3/A19 R5 PC4/A20 T4 PC5/A21 P5 PC6/A22/nFWE R4 PC7/A23/nFRE P15 PD0/D8 P14 PD1/D9 N13 PD2/D10 T15 PD3/D11 N12 ...
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LH79524/LH79525 Table 2. LH79524 Pin Descriptions (Cont’d) LFBGA SIGNAL NAME TYPE PIN A7 PG5/LCDVD3 C8 PG6/LCDVD4 B8 PG7/LCDVD5 C4 PH0/ETHERRX3 A3 PH1/ETHERRXDV B4 PH2/ETHERRXCLK C5 PH3/ETHERTXER D6 PH4/ETHERTX0 A4 PH5/ETHERTX1 B5 PH6/ETHERTX2 C6 PH7/ETHERTX3 D3 PI0/ETHERMDC B1 PI1/ETHERMDIO B2 PI2/ETHERCOL ...
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System-on-Chip Table 2. LH79524 Pin Descriptions (Cont’d) LFBGA SIGNAL NAME TYPE PIN P11 PN3/D25 J2 nRESETIN H1 nRESETOUT C16 XTALIN C15 XTALOUT D16 XTAL32IN D15 XTAL32OUT K1 CLKOUT D2 nTRST P4 TMS T3 TCK T1 TDI P3 TDO T2 TEST1 ...
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LH79524/LH79525 Table 3. LH79524 Numerical Pin List LFBGA FUNCTION MULTIPLEXED NO. AT RESET FUNCTION(S) A1 PI5 ETHERRX0 A2 PI6 ETHERRX1 A3 PH1 ETHERRXDV A4 PH5 ETHERTX1 A5 PG0 ETHERTXEN A6 PG2 LCDVD0 A7 PG5 LCDVD3 A8 PF0 LCDVD6 A9 PF1 ...
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System-on-Chip Table 3. LH79524 Numerical Pin List (Cont’d) LFBGA FUNCTION MULTIPLEXED NO. AT RESET FUNCTION(S) G13 VDD G14 DQM3 G15 SDCKE G16 nDCS0 H1 nRESETOUT H2 AN3/LR/Y- PJ0 H3 AN4/WIPER PJ1 H4 VDD H7 VSS H8 VSS H9 VSS H10 ...
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LH79524/LH79525 Table 3. LH79524 Numerical Pin List (Cont’d) LFBGA FUNCTION MULTIPLEXED NO. AT RESET FUNCTION(S) P8 A11 P9 A6 P10 A3 P11 PN3 D25 P12 PD6 D14 P13 PK4 D20 P14 PD1 D9 P15 PD0 D8 P16 D5 DREQ/ R1 ...
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System-on-Chip PIN NO. SIGNAL NAME TYPE A10 67 A11 65 A12 63 A13 62 A14 61 A15 99 ...
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LH79524/LH79525 Table 5. LH79525 Pin Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE 20 AN3/LR/Y–/PJ0 I 19 AN4/WIPER/PJ1 I 15 AN5/PJ5/INT5 I 12 AN6/PJ7/INT7 I 13 AN7/PJ6/INT6 I 16 AN8/PJ4 I 18 AN9/PJ2 I CTCLK/INT4/ 25 I/O BATCNTL PA0/UARTRX2/ 36 I/O ...
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System-on-Chip Table 5. LH79525 Pin Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE 53 PC6/A22/nFWE I/O 52 PC7/A23/nFRE I/O 90 PD0/D8 I/O 89 PD1/D9 I/O 88 PD2/D10 I/O 87 PD3/D11 I/O 85 PD4/D12 I/O 84 PD5/D13 I/O 83 PD6/D14 I/O 82 ...
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LH79524/LH79525 Table 5. LH79525 Pin Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE 163 PH7/ETHERTX3 I/O 4 PI0/ETHERMDC I/O 2 PI1/ETHERMDIO I/O 1 PI2/ETHERCOL I/O 176 PI3/ETHERCRS I/O 175 PI4/ETHERRXER I/O 174 PI5/ETHERRX0 I/O 173 PI6/ETHERRX1 I/O 172 PI7/ETHERRX2 I/O 24 ...
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System-on-Chip Table 6. LH79525 Numerical Pin List (Cont’d) PIN FUNCTION MULTIPLEXED NO. AT RESET FUNCTION(S) 3 VDD 4 PI0 ETHERMDC 5 VSS 6 VDDC 7 VSSC 8 nTRST 9 LINREGEN 10 VDDA0 11 AN0/UL/X+ 12 AN6 PJ7/INT7 13 AN7 PJ6/INT6 ...
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LH79524/LH79525 Table 6. LH79525 Numerical Pin List (Cont’d) PIN FUNCTION MULTIPLEXED NO. AT RESET FUNCTION( 100 nCS3 PM3 101 VDD 102 nCS2 PM2 103 nCS1 PM1 104 nCS0 PM0 105 VSSC 106 nOE 107 ...
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System-on-Chip Table 7. TESTx PIN FUNCTION MODE TEST1 Embedded ICE 0 Normal 1 LFBGA LFBGA MONO 4-BIT BALL BALL NAME NO. SINGLE PANEL C2 LCDVD15 MUSTN0 C1 LCDVD14 X C10 LCDVD13 X A10 LCDVD12 X A11 LCDVD11 X B10 LCDVD10 ...
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LH79524/LH79525 Table 9. LH79525 LCD Data Multiplexing STN MONO 4-BIT PIN NO. PIN NAME SINGLE PANEL 157 LCDVD2 158 LCDVD1 MUSTN3 159 LCDVD0 MUSTN2 WIRELESS ROUTER/ SWITCHER CODEC Figure 4. LH79524/LH79525 Application Diagram Example SYSTEM DESCRIPTIONS ARM720T Processor The LH79524/LH79525 ...
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System-on-Chip External Memory Controller An integrated External Memory Controller (EMC) provides a glueless interface to external SDRAM, Low Power SDRAM, Flash, SRAM, ROM, and burst ROM. Three remap options for the physical memory are selectable by software, as shown in ...
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LH79524/LH79525 0xFFFFFFFF ADVANCED HIGH-PERFORMANCE BUS PERIPHERALS 0xFFFF1000 RESERVED 0xFFFF0000 ADVANCED PERIPHERAL BUS PERIPHERALS 0xFFFC0000 RESERVED 0xA0000000 BOOT ROM 0x80000000 16KB INTERNAL SRAM 0x60000000 EXTERNAL STATIC MEMORY 0x40000000 EXTERNAL SDRAM 0x20000000 EXTERNAL SRAM nCS0 0x00000000 REMAP = 11 Figure 8. Memory ...
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System-on-Chip Universal Asynchronous Receiver Transmitter (UART) The LH79524/LH79525 incorporates three UARTs. UART0, UART1, and UART2 offer similar functionality to the industry-standard 16C550. They perform serial- to-parallel conversion on data received from a periph- eral device and parallel-to-serial conversion on data ...
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LH79524/LH79525 Table 10. Interrupt Channels (Cont’d) CHANNEL INTERRUPT SOURCE 18 ADC Pen IRQ 19 CLCD Combined Interrupt 20 DMA Stream 0 21 DMA Stream 1 22 DMA Stream 2 23 DMA Stream SSP I S Interrupt 25 ...
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System-on-Chip Watchdog Timer The Watchdog Timer provides hardware protection against malfunctions programmable timer to be reset by software at regular intervals. Failure to reset the timer will cause a FIQ interrupt. Failure to service the FIQ interrupt ...
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LH79524/LH79525 Ethernet MAC Controller The on-board Ethernet MAC Controller (EMAC) is compatible with IEEE 802.3, and has passed the Uni- versity of New Hampshire (UNH) testing. It supports both 10- and 100-Mbit/s, and full and half duplex oper- ation. Other ...
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System-on-Chip ADC and Brownout Detector The ADC block consists of an 10-channel, 10-bit Analog-to-Digital Converter with integrated Touch Screen Controller (TSC). The complete touch screen interface is achieved by combining the front-end bias- ing, control circuitry with analog-to-digital conversion, reference ...
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LH79524/LH79525 Power Supply Sequencing When the linear regulator is not enabled, NXP rec- ommends that the 1.8 V power supply be energized before the 3.3 V supply. If this is not possible, the 1.8 V supply may not lag the ...
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System-on-Chip AC Test Conditions PARAMETER Supply Voltage (VDD) Core Voltage (VDDC) Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Power Consumption By Peripheral Device Table 13 shows the typical power consumption by individual peripheral ...
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LH79524/LH79525 SIGNAL TYPE LOAD SYMBOL ASYNCHRONOUS MEMORY INTERFACE SIGNALS Output 50 pF A[27:0] Input tDHWE tDWE tDSCS D[31:0] Output 50 pF tDSOE tDSB tDHCS tDHOE tAHCS tAHOE nCS[3:0] Output 50 pF tASCS tAHB tDHBR tDHBW nBLE Output 50 pF tASB ...
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System-on-Chip Table 14. AC Signal Characteristics (Cont’d) SIGNAL TYPE LOAD SYMBOL tOVSDW nWE Output 30 pF tOHSDW tOVC0 SDCKE Output 30 pF tOHC0 tOVDQ DQM[3:0] Output 30 pF tOHDQ tOVSC nSDCS[1:0] Output 30 pF tOHSC SDCLK Output 30 pF tSDCLK ...
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LH79524/LH79525 Analog-To-Digital Converter Electrical Characteristics Table 15 shows the ADC electrical characteristics. See Figure 10 for the ADC transfer characteristics. Table 15. ADC Electrical Characteristics PARAMETER A/D Resolution Throughput Conversion Acquisition Time Data Format CLK Frequency Differential Non-Linearity Integral Non-Linearity ...
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System-on-Chip 1024 1023 1022 1021 1020 1019 1018 9 8 CENTER OF A STEP OF THE ACTUAL 7 TRANSFER CURVE LSB OFFSET ERROR DNL Product data sheet NXP Semiconductors IDEAL ...
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LH79524/LH79525 External Memory Controller Waveforms The External Memory Controller (EMC) handles transactions with both static and dynamic memory. STATIC MEMORY WAVEFORMS This section illustrates static memory transaction waveforms. Each wait state is one HCLK period. nWAIT Input The EMC’s Static ...
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System-on-Chip tDA_nCS(x)_nWAIT nCS(x) nOE nWAIT SQ-4 SQ-3 HCLK Transaction WST-3 WST-2 Sequence DELAY DELAY NOTES: SQ: nWAIT Sampled and Queued SI: nWAIT Sampled and Ignored Figure 11. nWAIT Read Sequence (SWAITRDx = 3) Table 16. nWAIT Read Sequence Parameter Definitions ...
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LH79524/LH79525 tDA_nCS(x)_nWAIT nCS(x) nOE nWAIT SI SI SQ-4 HCLK Transaction WST-5 WST-4 WST-3 Sequence DELAY DELAY DELAY NOTES: SQ: nWAIT Sampled and Queued SI: nWAIT Sampled and Ignored Figure 12. nWAIT Read Sequence (SWAITRDx = 5) tDA_nCS(x)_nWAIT nCS(x) nOE nWAIT ...
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System-on-Chip tDA_nCS(x)_nWAIT nCS(x) nWE nWAIT SQ-4 SQ-3 HCLK Transaction WST-3 WST-2 Sequence DELAY DELAY NOTES: SQ: nWAIT Sampled and Queued SI: nWAIT Sampled and Ignored Figure 14. nWAIT Write Sequence (SWAITWRx = 3) Table 17. nWAIT Write Sequence Parameter Definitions ...
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LH79524/LH79525 tDA_nCS(x)_nWAIT nCS(x) nWE nWAIT SI SI SQ-4 HCLK Transaction WST-5 WST-4 WST-3 Sequence DELAY DELAY DELAY NOTES: SQ: nWAIT Sampled and Queued SI: nWAIT Sampled and Ignored Figure 15. nWAIT Write Sequence (SWAITWRx = 5) tDA_nCS(x)_nWAIT nCS(x) nWE nWAIT ...
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System-on-Chip tASCS HCLK A[23:0] D[31:0] nCS tOEV nOE tBV nBLEx Figure 17. External Static Memory Read, Zero Wait States Product data sheet NXP Semiconductors tRC tDSB tDSCS, tDSOE tAHCS, tAHOE tAHB VALID ADDRESS VALID DATA tCS tOE tDHCS tDHBR tDHOE ...
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LH79524/LH79525 HCLK A[23: 0] tASCS D[ 31:0 ] nCS nWE tASB nBLEx Figure 18. External Static Memory Write, Zero Wait States HCLK A[23:0] D[31:0] nCSx nOE Figure 19. External Static Memory Read with Three Wait States 40 NXP Semiconductors tWC ...
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System-on-Chip HCLK A[23:0] D[31:0] nCSx nWE or nBLEx Figure 20. External Static Memory Write with Two Wait States Product data sheet NXP Semiconductors tWC VALID ADDRESS VALID DATA Rev. 02 — 17 March 2009 LH79524/LH79525 LH79525-73 41 ...
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LH79524/LH79525 SDRAM MEMORY CONTROLLER WAVEFORMS Figure 21 shows the waveform and timing for an SDRAM Burst Read (page already open). Figure 22 shows the waveform and timing for SDRAM to Activate a Bank and Write. t SDCLK SCLK SDRAMcmd DQMx ...
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System-on-Chip Figure 22. SDRAM Bank Activate and Write Product data sheet NXP Semiconductors Rev. 02 — 17 March 2009 LH79524/LH79525 43 ...
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LH79524/LH79525 External DMA Handshake Signal Timing DREQ TIMING Once asserted, DREQ must not transition from LOW to HIGH again until after nDACK has been asserted. NOTE: tDREQ0L = DREQ0 LOW Pulse Width = 2 HCLK MIN. tDREQ1L = DREQ1 LOW ...
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System-on-Chip HCLK (See Note) A[23:0] D[15:0] nCSx nWEN nBLE[1:0] nOE DACK0/ DEOT0/DEOT1 nDACK1 NOTE: * HCLK is an internal signal provided for reference only. Figure 25. Write, from Memory to Peripheral, Burst Size = 1 * HCLK ADDRESS A[23:0] D[31:0] ...
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LH79524/LH79525 Figure 27. Write, Memory-to-Peripheral: Burst Size = 4; Destination Width > External Access Width 46 NXP Semiconductors Rev. 02 — 17 March 2009 System-on-Chip Product data sheet ...
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System-on-Chip Color LCD Controller Timing Diagrams Product data sheet NXP Semiconductors Figure 28. STN Horizontal Timing Rev. 02 — 17 March 2009 LH79524/LH79525 47 ...
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LH79524/LH79525 48 NXP Semiconductors Figure 29. STN Vertical Timing Rev. 02 — 17 March 2009 System-on-Chip Product data sheet ...
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System-on-Chip Product data sheet NXP Semiconductors Figure 30. TFT Horizontal Timing Rev. 02 — 17 March 2009 LH79524/LH79525 49 ...
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LH79524/LH79525 50 NXP Semiconductors Figure 31. TFT Vertical Timing Rev. 02 — 17 March 2009 System-on-Chip Product data sheet ...
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System-on-Chip * CLCDCLK (INTERNAL) APBPERIPHCLKCTRL1:LCD AD-TFT and HR-TFT SIGNALS ARE TFT SIGNALS, RE-TIMED CLKPRESCALE:LCDPS (SHOWN FOR REFERENCE) TIMING0:HSW LCDLP (HORIZONTAL SYNCHRONIZATION PULSE) LCDDCLK (PANEL CLOCK) TIMING2:PCD TIMING2:BCD TIMING2:IPC TIMING2:CPL LCDVD[11:0] (LH79525) LCDVD[15:0] (LH79524) 16 × (TIMING0:PPL+1) LCDEN (INTERNAL DATA ENABLE) ...
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LH79524/LH79525 Synchronous Serial Port The SSP timing is illustrated in Figure 34. Figure 34. Synchronous Serial Port Waveform 52 NXP Semiconductors Rev. 02 — 17 March 2009 System-on-Chip Product data sheet ...
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System-on-Chip Ethernet MAC Controller Waveforms The timing for the EMC is presented in the following two illustrations. Figure 35 shows an Ethernet transmit and Figure 36 shows an Ethernet receive. ETHERTXCLK ETHERTXER, ETHERTX[3:0], ETHERTXEN ETHERRXCLK ETHERRXDV, ETHERRX[3:0] Product data sheet ...
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LH79524/LH79525 Reset, Clock, and Power Controller (RCPC) Waveforms Figure 37 shows the method the LH79524/LH79525 uses when coming out of Reset or Power On. PARAMETER tOSC32 Oscillator stabilization time after Power Up (VDDC = VDDCMIN) Oscillator stabilization time after Power ...
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System-on-Chip UNUSED INPUT SIGNAL CONDITIONING Floating input signals can cause excessive power consumption. Unused inputs which do not include inter- nal pull-up or pull-down resistors should be pulled up or down externally, to tie the signal to its inactive state. ...
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LH79524/LH79525 INTERNAL TO THE LH79524/LH79525 EXTERNAL TO THE LH79524/LH79525 NOTES parallel-resonant type crystal. (See table) 2. The nominal values for C1 and C2 shown are for a crystal specified load capacitance (CL). 3. ...
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System-on-Chip PACKAGE SPECIFICATIONS LQFP176: plastic low profile quad flat package; 176 leads; body 1 132 133 pin 1 index 176 DIMENSIONS (mm are the original dimensions) ...
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LH79524/LH79525 LFBGA208: plastic low profile fine-pitch ball grid array package; 208 balls ball A1 index area ball ...
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System-on-Chip NOTE: Dimensions in mm. Figure 43. LH79525: LQFP176 PCB Footprint 208-BALL CABGA TOP VIEW A1 BALL PAD CORNER NOTES: 1.00 1. Dimensions in ...
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LH79524/LH79525 REVISION HISTORY Document ID Release date Data sheet status LH79524_525_N_2 20090317 Modifications: • Changed document status to “Product data sheet”. LH79524_525_N_1 20070716 60 NXP Semiconductors Table 19. Revision history Change notice Product data sheet - Preliminary data - sheet ...
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System-on-Chip 9. Legal information 9.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or completing ...
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Dear customer from June 1 , 2007 NXP Semiconductors has acquired the LH7xxx ARM Microcontrollers from Sharp Microelectronics. The following changes are applicable to the attached data sheet. In data sheets where the previous Sharp or Sharp Corporation ...
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ANNEX A: Disclaimers (11) 1. t001dis100.fm: General (DS, AN, UM) General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied the accuracy ...
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No offer to sell or license (DS) No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance ...