LH79525N0Q100A1 Sharp Electronics, LH79525N0Q100A1 Datasheet - Page 35
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LH79525N0Q100A1
Manufacturer Part Number
LH79525N0Q100A1
Description
Manufacturer
Sharp Electronics
Datasheet
1.LH79525N0Q100A1.pdf
(64 pages)
Specifications of LH79525N0Q100A1
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Applications
Embedded Control
Processing Unit
Microcontroller
Operating Supply Voltage (min)
1.7/3V
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.9/3.6V
Package Type
LQFP
Screening Level
Industrial
Pin Count
176
Mounting
Surface Mount
Rad Hardened
No
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LH79525N0Q100A1
Manufacturer:
FREESCALE
Quantity:
101
Company:
Part Number:
LH79525N0Q100A1,55
Manufacturer:
NXP Semiconductors
Quantity:
10 000
System-on-Chip
NOTES:
1. The timing relationship is specified as a cycle-based timing. Variations caused by clock jitter, power rail noise, and I/O conditioning will cause
2. The Read Wait States register (SWAITRDx) must be set to a minimum value of 3.
3. For each rising clock edge (HCLK) that the assertion of nWAIT lags the assertion of nCSx, another read wait state (SWAITRDx) must be
4. nWAIT delay cycles are not added for all nWAIT assertions sampled prior to WST-3. These nWAIT assertions are ignored.
5. nWAIT delay cycles are added for all nWAIT assertions sampled from WST-3 until the de-assertion of nWAIT. nWAIT delay cycles are added
6. Once nWAIT is sampled high, the current memory transaction is queued to complete.
7. Since static and dynamic memory cannot be accessed at the same time, any prolonged access (either due to nWAIT or the Extended Wait
8. Timing assumes Output Enable Delay register (SWAITOENx) is programmed to 0.
Product data sheet
tDA_nCS(x)_nWAIT
tDD_nWAIT_nCS(x)
tDD_nWAIT_nOE
tA_nWAIT
NOTES:
SQ: nWAIT Sampled and Queued
SI: nWAIT Sampled and Ignored
these timings to vary nominally. It is recommended that designers add a small margin to avoid possible corner-case conditions.
added to the minimum requirement.
once the wait state countdown has reached WST-1.
Register) that causes an SDRAM refresh failure may cause SDRAM data to be lost.
nCS(x)
nWAIT
HCLK
Transaction
Sequence
nOE
PARAMETER
tDA_nCS(x)_nWAIT
DELAY
WST-3
Delay from nCS(x) assertion to nWAIT assertion
Delay from nWAIT deassertion to nCS(x) deassertion
Delay from nWAIT deassertion to nOE deassertion
Assertion time of nWAIT
SQ-4
Table 16. nWAIT Read Sequence Parameter Definitions
DELAY
WST-2
Figure 11. nWAIT Read Sequence (SWAITRDx = 3)
SQ-3
DELAY
WST-1
tA_nWAIT
SQ-2
Rev. 02 — 17 March 2009
NXP Semiconductors
DELAY
nWAIT
SQ-4
DESCRIPTION
SQ-1
DELAY
nWAIT
SQ-3
SQ-0
DELAY
nWAIT
SQ-2
DELAY
nWAIT
tDD_nWAIT_nCS(x)
SQ-1
tDD_nWAIT_nOE
DELAY
nWAIT
SQ-0
MIN.
0
2
DELAY
WST-0
16,365
MAX.
4
4
LH79524/LH79525
HCLK periods
HCLK periods
HCLK periods
HCLK periods
UNIT
LH79525-133
1
35