DSP56301AG100 Freescale, DSP56301AG100 Datasheet - Page 48

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DSP56301AG100

Manufacturer Part Number
DSP56301AG100
Description
Manufacturer
Freescale
Datasheet

Specifications of DSP56301AG100

Device Core Size
24b
Format
Fixed Point
Clock Freq (max)
100MHz
Mips
100
Device Input Clock Speed
100MHz
Ram Size
24KB
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
208
Package Type
TQFP
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSP56301AG100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Specifications
2-22
Notes:
No.
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
RAS assertion to row address not valid
Column address valid to CAS assertion
CAS assertion to column address not valid
RAS assertion to column address not valid
Column address valid to RAS deassertion
WR deassertion to CAS assertion
CAS deassertion to WR
RAS deassertion to WR
CAS assertion to WR deassertion
RAS assertion to WR deassertion
WR assertion pulse width
WR assertion to RAS deassertion
WR assertion to CAS deassertion
Data valid to CAS assertion (write)
CAS assertion to data not valid (write)
RAS assertion to data not valid (write)
WR assertion to CAS assertion
CAS assertion to RAS assertion (refresh)
RAS deassertion to CAS assertion (refresh)
RD assertion to RAS deassertion
RD assertion to data valid
RD deassertion to data not valid
WR assertion to data active
WR deassertion to data high impedance
1.
2.
3.
4.
Table 2-12.
The number of wait states for an out-of-page access is specified in the DCR.
The refresh period is specified in the DCR.
RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t
Either t
RCH
or t
RRH
Characteristics
4
4
DRAM Out-of-Page and Refresh Timings, Eight Wait States
assertion
assertion
must be satisfied for read cycles.
3
3
DSP56301 Technical Data, Rev. 10
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WCH
WCR
RCH
RRH
t
RWL
CWL
t
DHR
WCS
ROH
t
RAH
ASC
CAH
t
RAL
RCS
t
CSR
RPC
t
WP
AR
DS
DH
GA
GZ
1.75 × T
0.75 × T
3.25 × T
5.75 × T
1.25 × T
0.25 × T
8.75 × T
7.75 × T
4.75 × T
3.25 × T
5.75 × T
1.75 × T
0.75 × T
5.5 × T
8.5 × T
5.5 × T
1.5 × T
8.5 × T
7.5 × T
Expression
4 × T
2 × T
3 × T
0.25 × T
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
− 4.0
− 3.8
− 4.2
OFF
− 4.2
− 4.5
− 4.3
− 4.0
− 4.0
− 6.5
− 4.0
− 4.0
− 4.0
− 4.0
− 3.7
− 2.6
− 4.3
− 4.3
− 4.0
− 4.0
− 4.0
− 4.0
− 1.5
C
1, 2
and not t
(Continued)
Freescale Semiconductor
GZ
101.8
105.1
102.3
Min
17.9
36.6
67.9
46.0
21.2
11.9
33.3
64.6
92.6
55.4
36.6
67.9
64.5
14.8
17.9
5.4
0.5
0.0
7.9
.
80 MHz
Max
87.3
3.1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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