MCIMX31LCVKN5D Freescale, MCIMX31LCVKN5D Datasheet - Page 36

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MCIMX31LCVKN5D

Manufacturer Part Number
MCIMX31LCVKN5D
Description
Manufacturer
Freescale
Datasheet

Specifications of MCIMX31LCVKN5D

Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant

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1
2
Electrical Characteristics
4.3.9
This section provides electrical parametrics and timings for EMI module.
4.3.9.1
The NFC supports normal timing mode, using two flash clock cycles for one access of RE and WE. AC
timings are provided as multiplications of the clock cycle and fixed delay.
and
for normal mode, and
36
Phase lock time
Maximum allowed PLL supply voltage ripple
Maximum allowed PLL supply voltage ripple
Maximum allowed PLL supply voltage ripple
PLL output clock phase jitter
PLL output clock period jitter
The user or board designer must take into account that the use of a frequency other than 26 MHz would require adjustment to
the DPTC–DVFS table, which is incorporated into operating system code.
The PLL reference frequency must be ≤ 35 MHz. Therefore, for frequencies between 35 MHz and 70 MHz, program the
predivider to divide by 2 or more. If the CKIH frequency is above 70 MHz, program the predivider to 3 or more. For PD bit
description, see the reference manual.
Figure 25
EMI Electrical Specifications
NAND Flash Controller Interface (NFC)
depict the relative timing requirements among different signals of the NFC at module level,
NFCLE
NFCE
NFWE
NFALE
NFIO[7:0]
Parameter
Table 31
Figure 22. Command Latch Cycle Timing DIagram
lists the timing parameters.
Table 30. DPLL Specifications (continued)
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
NF6
NF3
NF1
Min
Command
NF8
NF5
Typ
NF9
NF7
Max
100
420
5.2
NF2
25
20
25
NF4
Unit
mV F
mV 50 kHz < F
mV F
ns
ps
µs
Figure
In addition to the frequency
Measured on CLKO pin
Measured on CLKO pin
modulation
modulation
22,
< 50 kHz
> 300 kHz
Figure
modulation
Freescale Semiconductor
Comments
23,
< 300 kHz
Figure
24,

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