MC68882RC25A Freescale, MC68882RC25A Datasheet - Page 18

• Manufacturer Part Number: MC68882RC25A
• Manufacturer: Freescale

Specifications of MC68882RC25A

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

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MOTOROLA
18
All signals
the parameters
&,:,?:**~:4
lays, input setup and hold times, and signal skew times,
ef the clock input and, possibly,
other signals.
by the waveforms
driven to the voltage levels specified
AC ELECTRICAL
NOTES:
,+~,. .,
,+,: <,i,:.,i
The AC specifications
The measurement
253S8
2j3,8
233,8
Num
13A4
19A7
2. These specifications
3. Synchronous
4. This specification only ap#}?&s~W->ystemsin which back-to-back accesses (read-write or write-write) of the operand CIR can
5. If the SIZE pin is g~~~~mped
6. If the SIZE pin i/’~t#rapped
7. This numbW?~,~edu~ed
8. START is ti~~iw~xternal
9. If a ~’~k~~~$nt
1. Timing
218
228
243
263
ELECTRICAL
142
192
20
13
15
16
17
18
g~u~s~ot
‘{$>$.
12
,y.lw, ,.*
occur. When
this c~,~~~~o ~ m=
Tk@#@’~cifications
noted, The voltage
linear between 0.8 volts and 2.o
bus cycle when ~
Immediate.
}}
~
=
~,
~
~
~
—
START False to DSACKO and DSACK1 Negated
START False to DSACKO and DSACKI
START True to Clock High (Synchronous
Clock Low to Data-Out Valid (Synchronous
START True to Data-Out Valid (Synchronous
Clock Low to DSACKO and DSACKI
START
~
Data-In Valid to ~
START True to DSACKO and DSACK1 Asserted
DSACKO Asserted
DSACKO or DSACKI
are specified
(Synchronous
(Synchronous
measurements
Width Asserted {Write)
Width Negated
Negated to ~
Negated to Data-Out Invalid
Negated to Data-Out High Impedance
Negated
~
occur simultaneously
guaranteed
True to DSACKO
SPECIFICATION
Asserted
SPECIFICATIONS
the MC6w&~,$@sed
read cycles
shown
access is not a FPCP access, ~
—
to Data-In Invalid
of the AC specifications
swing through
was negated~tl, .~, ~~
—
—
—
only apply if $&$*~882
.~~:
replace the old specifications
presented
relative to an appropriate
Read)
Read)
to Data-Out Valid) (Read)
$ *.{:&$
to DSACKI
are referenced
Asserted
in Figure 20. In order to test
to 5 nanoseconds
Asserted
Characteristic
by Motorola,
Freescale Semiconductor, Inc.
~
Asserted
occ~:$o~’when
signal;
For More Information On This Product,
+~
and DSACK1
relative to one or more
to either VCC or GND, it must have the same setup times as do addresses.
to either VCC or GND, it must have the same hold times as do addresses.
DEFINITIONS
with transitions
vol~
— READ AND
_
consist of output
rather, it is the logical condition
‘“:;$.’:
—
—
t R~*~.
in. Figure 20. Outputs
(Write)
this&@~~$~$~ould
Asserted
to Data-Out Valid
(Write)
as a coprocessor
::<~j:.
(Read)
“ii~(,:}’
to ~~,.~~m”’a
Go to: www.freescale.com
inputs must be
Asserted
High Impedance
As5~~ted
if DSACKO and DSACKI
the save or response CIR locations are read.
t:~,. ~,
(Skew)
—
,+:~~$,{
is defined
Read)
has completed
(Read)
**>..
must be negated
of ~
(~j,
Read)
>
WRITE
Read)
edge
8 and 8A (the old specifications
start outside,
: ‘
de-
low voltage
to the MC68020/MC68030,
or ~.
*,~,\::<.,
“*7,!..
“<$ 1.5
‘+$> \Jli) ~,i,.$
CYCLES
—
.x.,*_
,J>,,
. . . . .
,, ~ii \
.. ~..>,i:
Min
–15
16.67 MHz
1.p:(,
40
—
—
—
—
—
—
—
—
This is not a.requirement
40
30
15
15
o
all internal
~>~
are specified
appropriate,
specified
setup and hold times,
are also shown.
to the AC specifications
characteristics.
nally, the measurement
DC operation
*$ ?’;~75
<i,
before the assertion
Note that the testing
of 0.8 volts and a high voltage
.
that indicates
and pass through,
, ~,g
75+
Max
(Continued)
have equal loads.
l,g
2.5 ‘
2.5
—
50
70
—
—
—
80
—
50
—
50
15
50
!
-
;,, ,$
*“_
operations
with minimum
Min
–lo
1.5
—
—
1.5
—
—
—
—
38
38
30
—
10
10
o
20 MHz
with
and are measured
of the device as specified in the DC electrical
the start of an access. The logical equation
this can occur
80+
55+
Max
2.5
2.5
35
43 ,j;~ :,<p~s
80
55
—
—
—
60
—
30
—
—
10
minimum
initiated
implied
the range such that the rise or fall will be
of ~
“ –
of the MC68882).
levels used to verify conformance
Min
- $*., $:.10 ‘
and are measured
—
1.5
—
—
1.5
for signal-to-signal
—
—
— ,$ ‘$~b,. i–
—
30
30
25
o
o
5
5
25 MHz
does not affect the guaranteed
and, as appropriate,
end/or ~
that in all cases, transitions
by the termination
60+
45+
and/or maximum
Max
when the addressing
2.5
2.5
32
30
40
—
60
45
—
—
—
45
—
30
—
~<:~ ‘(~’
of 2.0 volts, unless otherwise
7
as shown.
.—
:$ &~~:~ -
on the non-FPCP acce~
Min
33.33 MHz
–
—
—
–
—
1.5
—
—
1.5
23
23
—
18
o
o
45+
30+
Max
2.5
2.5
as shown,
specifications
–
20
20
30
—
45
30
—
—
—
17
5
of the previous
BR~/Rev.
,.
Inputs
maximum
..,,
limits, as
MC6B682
mode is
Unit
C;:s
CY:S
ns
ns
ns
ns
ns
ns
n5
ns
n5
ns
ns
ns
ns
in CS.
are
Fi-
for
. . . . ... . ,.,.,..
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r
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v
x.-..
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