MC68882RC25A Freescale, MC68882RC25A Datasheet - Page 5

• Manufacturer Part Number: MC68882RC25A
• Manufacturer: Freescale

Specifications of MC68882RC25A

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

~i%{e$~ests for any additional
“$.@~C68030
transfers,
‘%sponse may request that the MC68020 or MC68030 fetch
(BIU), the conversion
essing
and the MC68882 occur via standard
MC68620 or MC68030, the CU performs
For binary
MC68882 instructions.
(CIRS). In addition
and DSACK timing
Finally,
communications
in the BIU.
forms data format
formats
CU relieves the APU of a significant
the MC68882 to execute data movement
functions
tal calculations,
and the 32-bit
registers
In addition
speed 67-bit arithmetic
exponent
erator, a two-level
functions
16-, or 32-bit data buses.
face registers (CIRS) that ar~.~~r$ised
the,i@tru$~on
1 bit to 67 bits
(for use by the internal
ROM, and self-test
bilities of the MC68882 enhance reliability
ufacturing
ner as memory
coprocessor
reading
cessor. The MC6@:~0 anfl MC68030 implement
eral purpose
and microc~$~,$~~~ ~
MC68&Q~~~s?tuction,
r~S&%l~&response
an operand
transfer
the MC68020
subsequent
and any other bus transfer is that the MC68020 or MC68030
issues a CPU address
MC68020 or MC68030 fulfills
‘+’:t .:.:.~’:~’.t~.
The BIU contains
All communications
The CU contains
The eight 80-bit floating-point
The control
The MC68882 contains
WhenJh*~$~&68020
The only difference
unit
the status flags
to and from ‘the internal
and writing
(FPCR, FPSR and FPIAR) are located in the APU.
the operand
concurrently
calculations,
are not accessible
real data formats,
The MC68882
to these registers,
requirements;
instructions.
on behalf of the MC68882. For example,
(APU).
from
interface.r$<!#~@emented
co~ra$~ssor
section of the APU contains the clock gen-
to the memory-mapped
or MC68030
in one machine cycle, and ROM
by the rnai~~~~essor.
control,
~’ ‘ .:!$ , ~~ ..+
with the main processor
conversions
to these registers,
the evaluated
microcode
CIR. In this response, the BIU encodes
control
special
circuitry.
the coprocessor
The BIU communicates
t$$~#se
between a coprocessor
unit (CU), and the arithmetic
between the MC68@~~OFWC68030
or MC68030 detects a general type
the MC68020
with arithmetic
a barrel shifter that can shift from
algorithms
space function
unit used for both mantissa
to the operand
status,
used to monitor
a nu@b#~.~coprocessor
is design,~t~~~~~erate
interface
action required of the MC68020
logic is contained
is free to fetch and execute
purpose
however,
the coprocessor
Freescale Semiconductor, Inc.
The built-in
outside
registers
and the APU executes
sequencer,
the APU contains
between
and instruction
For More Information On This Product,
data registers
p?
effective
extended
:f},\,.*7. ~:
work load and allows
or user programs).
protocol
>~$iy,
M@~~Q:@>amily bus
hardware
or MC68030
The M68000 Family
of the special test ‘t
interface
the register
command
these
and transcenden-
.\\<..
in the same man-
via a protocol
by the main pro-
code during
data conversion
and preparation
binary real data
CIR. Once the
Go to: www.freescale.com
the microcode
and ease man- S+~&.$@’iformance can be selected
self-test
are contained
,,
the status
address
format.
s~i;,y+,.>~.
in hardware
bus transfer
diagnost~~~%k~
in the BIU.
request(s),
constants
(FPO-FP7)
with
that per-
registers
this gen-
address
CIR and
a high-
on 8-,
writes
select
capa-
proc-
inter-
The
and
and
the
the
the
all
of
of
: Weti
,J,~$&~~mperformance
cycle. (The function
spaces.)” Thus, the memory-mapped
face registers
three of the upper address lines during
tion code, is decoded to select one of eight coprocessor
ware when the MC68882 is used as a perl,~~:~~ktiith
to an exception
Family
address spaces. The MC68020 or MC68030
processor
cesses. This ID, along with the CPU address space func-
in the system.
on bus transfers,
processor capable of memory-mapped
style bus. When used as a periphe$$.@r@ssor
8-bit MC68008, the 16-bit MC68,R{:~$r?he
MC68882 instructions
ware emulation
be totally
vide a performancetW~~.@
by changing
next
slower (or faster) clock speeds than the MPU clock.
COPROCESSOR INTERFACE
The interface
so that the MC68020 or MC68030 does not have to corn-
does not have to duplicate
vides an orthogonal
time exception
the MPU and coprocessor
fully supported
MC68030. Th,~~pftMre
MC6803@s”’:?JW’
ru~.at~g
performance
part of the MC68882 and MC68020 or MC68030 designs.
pletely decode coprocessor
as effective
permitting
or MC68030 addressing
a single chip.
instructions
MC68020 or MC68030 instructions,
pletelytransparent
MC68030 single-step
coprocessor
mits coprocessor
never
MC68020
results. In this manner,
bit data bus provides high speed transfer of floating-point
operands
MC68882.
Since the coprocessor
Sin@’J%&$s
The M68000 Family coprocessor
While the execution
While
gener&k$&#$eq
CPU performance
a bus master.
processors
the M68000
transparent%~~:t~&Wser.
same clock speed as the main processor.
and results while simplifying
or MC68030 fetch all operands
ID field from the coprocessor
MC68882
address
may be overlapped
interface.
partitions
the ‘T~%~@’*processors to the MC68020
specifications,
do not infringe
traps. Thus, from the programmer’s
handler at g$$cut?~n time. Thus, the soft-
of the c~~~~~$~or
by the MC68882 and the M68000 Family
is asynchronous,
the protocol
to the programmer.
to be bus masters,
to identify
codes are generated
may therefore
and program
extension
uipment
evaluation).
instructions
are trapp~$:$
Family
The MC68882
of the great majority
MPU and coprocessor
modes and to generate execution
interface protocol
migrates
the MC68020 and MC68030
requirement,
main processor functions
instructions,
appear to be integrated
for MC68000-based
coprocessor
is easily ernu~?~q~~y
running
upon
to meet
using
of the instruction
eight
The MC68882 can pre-
the MC68882 need not
without
with
to utilize all MC68020
This partitioning
flow (trace) modes are
interface is an integral
interface
be customized.
concurrency
the main processor
instruction
coprocessor
@+@yaTan M68000
separate
the
requests
the floating-point
The MC68020 and
the MC68882
the execution
and the MC68882
the design of the
the MC68882
instruction
coprocessor
Particular
by the M68000
is ba~~wlely
change to the
interface
MC68020
.MC68010, all
and store all
protocol
places a co-
of MC68882
operations
with the
that
address
designs
~ ~~~.~l,
or data
is com-
set by
Price/
inter-
view,
Total
(such
For a
onto
soft-
onto
pro-
per-
any
can
ac-
the
32-
or
or
at
of
is