MCIMX255AJM4A Freescale, MCIMX255AJM4A Datasheet - Page 86

• Manufacturer Part Number: MCIMX255AJM4A
• Manufacturer: Freescale

Specifications of MCIMX255AJM4A

• Lead Free Status / RoHS Status: Compliant

1
3.7.9.2
The MDC frequency is designed to be equal to or less than 2.5 MHz to comply with the IEEE 802.3
standard MII specification. However the FEC can function correctly with a maximum MDC frequency of
15 MHz.
Figure 58
(M10—M15) shown in the figure.
86
M10
M11
M12
M13
M14
M15
M9
FEC_COL has the same timing in 10-Mbit 7-wire interface mode.
1
ID
ID
FEC_MDIO (output)
FEC_MDC (output)
FEC_MDIO (input)
FEC_MDC falling edge to FEC_MDIO output invalid (min.
propagation delay)
FEC_MDC falling edge to FEC_MDIO output valid (max.
propagation delay)
FEC_MDIO (input) to FEC_MDC rising edge setup
FEC_MDIO (input) to FEC_MDC rising edge hold
FEC_MDC pulse width high
FEC_MDC pulse width low
FEC_CRS to FEC_COL minimum pulse width
shows MII asynchronous input timings.
MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)
Figure 58. MII Serial Management Channel Timing Diagram
i.MX25 Applications Processor for Automotive Products, Rev. 4
Table 62. MII Asynchronous Inputs Signal Timing
Table 63. MII Serial Management Channel Timing
Characteristic
Characteristic
M12
M13
Table 63
M14
describes the timing parameters
Min.
1.5
Min.
40%
40%
M10
—
18
0
0
M11
M15
Max.
—
Max.
60%
60%
—
—
—
5
FEC_TX_CLK period
Freescale Semiconductor
FEC_MDC period
FEC_MDC period
Unit
Unit
ns
ns
ns
ns