MC9328MX1CVM15 Freescale, MC9328MX1CVM15 Datasheet

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... Mold Array Process-Ball Grid Array (MAPBGA). Figure 1 shows the functional block diagram of the i.MX1 processor. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2004, 2005, 2006. All rights reserved. Document Number: MC9328MX1 Rev ...

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... VMMU Controller DMAC Bus AIPI 2 Human Interface (11 Chnl) Control EIM & eSRAM SDRAMC (128K) MC9328MX1 Technical Data, Rev. 7 Standard System I/O GPIO PWM Timer 1 & 2 RTC Watchdog Multimedia Multimedia Accelerator Video Port Analog Signal Processor LCD Controller 2 S) Module Freescale Semiconductor ...

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... Table 1. Ordering Information Temperature Solderball Type 0°C to 70°C Pb-free -30°C to 70°C Pb-free 0°C to 70°C Pb-free -30°C to 70°C Pb-free -40°C to 85°C Pb-free MC9328MX1 Technical Data, Rev. 7 Introduction based Order Number MC9328MX1VM20(R2) MC9328MX1DVM20(R2) MC9328MX1VM15(R2) MC9328MX1DVM15(R2) MC9328MX1CVM15(R2) 3 ...

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... SDBA [4:0] SDRAM non-interleave mode bank address multiplexed with address signals A [15:11]. These signals are logically equivalent to core address p_addr [25:21] in SDRAM cycles. 4 Table 2. i.MX1 Signal Descriptions Function/Notes External Bus/Chip-Select (EIM) Bootstrap SDRAM Controller MC9328MX1 Technical Data, Rev. 7 Freescale Semiconductor ...

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... Test Clock to synchronize test logic and control register access through the JTAG port. TMS Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge of TCK. Freescale Semiconductor Function/Notes Clocks and Resets JTAG MC9328MX1 Technical Data, Rev. 7 ...

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... Start signal output for gate driver. This signal is an inverted version of PS (Sharp panel dedicated signal). REV Signal for common electrode driving signal preparation (Sharp panel dedicated signal). SIM_CLK SIM Clock SIM_RST SIM Reset SIM_RX Receive Data 6 Function/Notes DMA ETM CMOS Sensor Interface LCD Controller SIM MC9328MX1 Technical Data, Rev. 7 Freescale Semiconductor ...

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... USB Analog Front End Enable SD_CMD SD Command—If the system designer does not wish to make use of the internal pull-up, via the Pull-up enable register, a 4.7K–69K external pull up resistor must be added. Freescale Semiconductor Function/Notes SPI 1 and SPI 2 General Purpose Timers USB Device Secure Digital Interface MC9328MX1 Technical Data, Rev ...

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... Data Set Ready UART3_RI Ring Indicator UART3_DCD Data Carrier Detect UART3_DTR Data Terminal Ready Serial Audio Port – SSI (configurable to I SSI_TXDAT Transmit Data SSI_RXDAT Receive Data 8 Function/Notes Memory Stick Interface UARTs – IrDA/Auto-Bauding 2 S protocol) MC9328MX1 Technical Data, Rev. 7 Freescale Semiconductor ...

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... Negative resistance input (b) RVP Positive reference for pen ADC RVM Negative reference for pen ADC AVDD Analog power supply AGND Analog ground BT1 I/O clock signal BT2 Output BT3 Input Freescale Semiconductor Function/Notes PWM ASP BlueTooth MC9328MX1 Technical Data, Rev. 7 Signals and Connections 9 ...

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... GPIO registers when those pins are multiplexed to provide different functions. 10 Function/Notes Test Function ® registered trademark of National Semiconductor.) Digital Supply Pins Supply Pins – Analog Modules Internal Power Supply Table 6 on page 23 Table 6 allows the user to select the function of each pin by MC9328MX1 Technical Data, Rev configure the Freescale Semiconductor ...

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... Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX1 Product Family Primary I/O Supply BGA Voltage ...

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... Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX1 Product Family Primary I/O Supply BGA Voltage ...

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... Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX1 Product Family Primary I/O Supply BGA Voltage ...

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... Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX1 Product Family Primary I/O Supply BGA Voltage ...

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... Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX1 Product Family Primary I/O Supply BGA Voltage ...

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... Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX1 Product Family Primary I/O Supply BGA Voltage ...

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... Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX1 Product Family Primary I/O Supply BGA Voltage ...

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... Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX1 Product Family Primary I/O Supply BGA Voltage ...

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... Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX1 Product Family Primary I/O Supply BGA Voltage ...

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... Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX1 Product Family Primary I/O Supply BGA Voltage ...

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... Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX1 Product Family Primary I/O Supply BGA Voltage ...

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... Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX1 Product Family Electrical Characteristics 3 Electrical Characteristics This section contains the electrical specifications and timing diagrams for the i.MX1 processor. ...

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... T Operating temperature range A MC9328MX1DVM20\MC9328MX1DVM15 T Operating temperature range A MC9328MX1CVM15 NVDD I/O supply voltage (if using MSHC, CSI, SPI, BTA, LCD, and USBd which are only 3 V interfaces) NVDD I/O supply voltage (if not using the peripherals listed above) QVDD Internal supply voltage (Core = 150 MHz) ...

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... Vdd DD – – 0.4 μA – – ±1 μA – – ±1 – – mA – – mA μA – – ±5 – – – – All L H Minimum Maximum Unit – 20.8 ns RMS Maximum Unit – – ms Freescale Semiconductor ...

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... A read or a write takes place when the TAP controller enters the UPDATE-DR state. The timing diagram for the ETM9 is shown in in Figure 2. TRACECLK TRACECLK (Half-Rate Clocking Mode) Output Trace Port Freescale Semiconductor Functional Description and Application Information Minimum 1 – TBD Figure 2. See Table 9 ...

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... T 300 (56 μs) ref 250 T 270 (50 μs) ref 350 T 400 (70 μs) ref 320 T 370 (64 μs) ref 0.005 2•T – 0.01 dck (0.01%) Freescale Semiconductor ...

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... Be aware that NVDD must ramp least 1.8V before QVDD is powered up to prevent forward biasing. 90% AVDD POR RESET_POR RESET_DRAM HRESET RESET_OUT CLK32 HCLK Figure 3. Timing Relationship with POR Freescale Semiconductor Functional Description and Application Information Test Conditions Minimum NOTE 1 10% AVDD 2 Exact 300ms 3 MC9328MX1 Technical Data, Rev. 7 ...

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... V Min Max 1 note 300 300 defines the parameters of signals. MC9328MX1 Technical Data, Rev cycles @ CLK32 4 3.0 ± 0.3 V Unit Min Max – 1 – – note 300 300 Cycles of CLK32 Cycles of CLK32 – 4 – Cycles of CLK32 Cycles of CLK32 Freescale Semiconductor ...

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... Table 12. EIM Bus Timing Parameter Table Ref No. Parameter 1a Clock fall to address valid 1b Clock fall to address invalid 2a Clock fall to chip-select valid 2b Clock fall to chip-select invalid 3a Clock fall to Read (Write) Valid 3b Clock fall to Read (Write) Invalid Freescale Semiconductor Functional Description and Application Information ...

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... Freescale Semiconductor ...

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... OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when EBC bit in CS5L register is clear. 3. Address becomes valid and CS asserts at the start of read access cycle. 4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state. Freescale Semiconductor Functional Description and Application Information 2 9 ...

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... OE negate after EB negate 11 Wait becomes low after CS5 asserted Minimum See note 2 3T 1.5T+0.24 – – 2T+2.2 T-1.86 – T 0.5 0 MC9328MX1 Technical Data, Rev 3.0 ± 0.3 V Unit Maximum – ns – ns 1.5T+0.85 ns 0.93 ns 1020T ns 3T+7.17 ns – – ns 1.5 ns 1019T ns Freescale Semiconductor ...

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... Characteristic 1 CS5 assertion time 2 EB assertion time 3 CS5 pulse width 4 RW negated before CS5 is negated 5 RW negated to Address inactive 6 Wait asserted after CS5 asserted Freescale Semiconductor Functional Description and Application Information Minimum 3.0 ± 0.3 V Minimum See note 2 See note ...

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... WAIT Write Cycle DMA Enabled Address 1 programmable min 0ns CS5 2 programmable min 0ns (logic high) 12 WAIT 9 DATABUS Figure 9. WAIT Write Cycle DMA Enabled 34 3.0 ± 0.3 V Minimum 1T+2.15 2.5T-1.18 – 1.5T+0. MC9328MX1 Technical Data, Rev. 7 Unit Maximum 2T+7.34 ns – 1.5T+2.35 ns 1019T ns 1020T Freescale Semiconductor ...

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... The External Interface Module (EIM) is the interface to devices external to the i.MX1, including generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown in Figure 5, and Table 12 defines the parameters of signals. Freescale Semiconductor Functional Description and Application Information 3.0 ± 0.3 V Minimum See note 2 See note 2 3T 2.5T-0.29 – ...

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... BCLK (burst clock) ADDR Last Valid Address CS2 R/W LBA EBx (EBC = EBx (EBC =1) DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register 36 Read V1 Last Valid Data Read Figure 10. WSC = 1, A.HALF/E.HALF MC9328MX1 Technical Data, Rev Freescale Semiconductor ...

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... BCLK (burst clock) Last Valid Address ADDR CS0 R/W LBA OE EB DATA Figure 11. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF Freescale Semiconductor Functional Description and Application Information V1 Write Data (V1) Last Valid Data Write Last Valid Data MC9328MX1 Technical Data, Rev. 7 Unknown V1 Write Data (V1) ...

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... R/W LBA EBx (EBC = EBx (EBC =1) DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 12. WSC = 1, OEA = 1, A.WORD/E.HALF 38 Address V1 Read 1/2 Half Word MC9328MX1 Technical Data, Rev Word Address 2/2 Half Word Freescale Semiconductor ...

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... BCLK (burst clock) ADDR Last Valid Addr CS0 R/W LBA OE EB DATA Figure 13. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MX1 Technical Data, Rev. 7 Address 2/2 Half Word ...

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... EBx (EBC =1) DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 14. WSC = 3, OEA = 2, A.WORD/E.HALF 40 Last Valid Data Address V1 Read 1/2 Half Word MC9328MX1 Technical Data, Rev Word Address 2/2 Half Word Freescale Semiconductor ...

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... Last Valid Addr CS3 R/W LBA OE EB DATA Last Valid Data Figure 15. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MX1 Technical Data, Rev. 7 Address 2/2 Half Word ...

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... EBx (EBC =1) weim_data_in Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 16. WSC = 3, OEA = 4, A.WORD/E.HALF 42 Last Valid Data Address V1 Read 1/2 Half Word MC9328MX1 Technical Data, Rev Word Address 2/2 Half Word Freescale Semiconductor ...

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... Last Valid Addr CS2 R/W LBA OE EB DATA Last Valid Data Figure 17. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MX1 Technical Data, Rev. 7 Address 2/2 Half Word ...

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... EBx (EBC =1) DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 18. WSC = 3, OEN = 2, A.WORD/E.HALF 44 Last Valid Data Address V1 Read 1/2 Half Word MC9328MX1 Technical Data, Rev Word Address 2/2 Half Word Freescale Semiconductor ...

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... EBx (EBC =1) DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 19. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Last Valid Data Address V1 Read 1/2 Half Word MC9328MX1 Technical Data, Rev. 7 ...

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... BCLK (burst clock) ADDR Last Valid Addr CS2 R/W LBA OE EB DATA Last Valid Data Figure 20. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF 46 Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MX1 Technical Data, Rev. 7 Unknown Address 2/2 Half Word Freescale Semiconductor ...

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... Last Valid Addr CS2 R/W LBA OE EB DATA Last Valid Data Figure 21. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MX1 Technical Data, Rev. 7 Unknown Address ...

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... Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 22. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF 48 Nonseq Write V8 Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MX1 Technical Data, Rev. 7 Write Data Read Data Address V8 Write Write Data Freescale Semiconductor ...

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... EBx (EBC =1) DATA DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 23. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF Freescale Semiconductor Functional Description and Application Information Read Idle Nonseq Write V8 Last Valid Data Address V1 Read ...

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... ADDR Last Valid Addr CS R/W LBA OE EB DATA Last Valid Data Figure 24. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF 50 Write Data (Word) Last Valid Data Address V1 Write Write Data (1/2 Half Word) MC9328MX1 Technical Data, Rev. 7 Address Write Data (2/2 Half Word) Freescale Semiconductor ...

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... EBx (EBC =1) DATA DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 25. WSC = 3, CSA = 1, A.HALF/E.HALF Freescale Semiconductor Functional Description and Application Information Nonseq Write V8 Last Valid Data Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MX1 Technical Data, Rev ...

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... Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 26. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF 52 Idle Seq Read V2 Read Data (V1) Address V1 CNC Read Read Data (V1) MC9328MX1 Technical Data, Rev. 7 Read Data (V2) Address V2 Read Data (V2) Freescale Semiconductor ...

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... EBx (EBC =1) DATA DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 27. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF Freescale Semiconductor Functional Description and Application Information Idle Nonseq Write V8 Last Valid Data Read Data Address V1 ...

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... EBx (EBC = EBx (EBC =1) ECB DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 28. WSC = 3, SYNC = 1, A.HALF/E.HALF 54 Nonse Read V5 Address V1 Read V1 Word V2 Word MC9328MX1 Technical Data, Rev. 7 Idle Address V5 V5 Word V6 Word Freescale Semiconductor ...

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... EBx (EBC =1) ECB DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 29. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD Freescale Semiconductor Functional Description and Application Information Seq Seq Read Read Word V2 Word Address V1 Read V1 Word ...

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... DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 30. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF 56 Seq Read V2 V1 Word Address V1 Read V1 1/2 V1 2/2 MC9328MX1 Technical Data, Rev. 7 Idle V2 Word Address V2 V2 1/2 V2 2/2 Freescale Semiconductor ...

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... EBx (EBC =1) ECB DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 31. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Seq Read Last Valid Data Address V1 Read V1 1/2 V1 2/2 MC9328MX1 Technical Data, Rev ...

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... Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 32. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF 58 Seq Read Last Valid Data Address V1 Read V1 1/2 V1 2/2 MC9328MX1 Technical Data, Rev. 7 Idle V2 V1 Word V2 Word V2 1/2 V2 2/2 Freescale Semiconductor ...

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... Pen ADC Specifications The specifications for the pen ADC are shown in Table 18. Pen ADC System Performance Full Range Resolution Non-Linearity Error Accuracy 1 Tested under input = 0~1.8V at 25°C Freescale Semiconductor Functional Description and Application Information T1 T3 XMAX Ts Figure 33. Non-TFT Panel Timing Allowed Register ...

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... Minimum Typical – 32768 – – – 13.65 – – – – – Negative QVDD – – 10 MC9328MX1 Technical Data, Rev. 7 Maximum Unit – – 8199 – – 33% – – Bits – Bits – Bits QVDD mV QVDD mV – Ohm Freescale Semiconductor ...

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... The ideal mapping of input voltage to output digital sample is defined as: -2400 In general, the mapping function is Where V is input output the slope, and C is the y-intercept. Nominal Gain G = 65535 / 4800 = 13.65mV 0 Nominal Offset C = 65535 / 2 = 32767 0 Freescale Semiconductor Functional Description and Application Information Sample 65535 Smax C0 1800 Figure 34. Gain Calculations -1 Sample 65535 ...

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... Figure 37 and Figure 38, and the associated parameters shown in 62 Sample Gmax 65535 Smax C0 1800 Figure 36. Gain Error Calculations = (65535 - C / 1800 0) = (65535 - 32767) / 1800 = 18. 100% max (18.20 - 13.65) / 13.65 * 100% = 33% CAUTION MC9328MX1 Technical Data, Rev 2400 Table 22 and Table 23. Freescale Semiconductor ...

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... Transmit Data hold time relative to RXTX_EN falling edge 1 Please refer to 2.4 GHz RF Transceiver Module (MC13180) Technical Data documentation. 2 The setup and hold times of RX_TX_EN can be adjusted by programming Time_A_B register (0x00216050) and RF_Status (0x0021605C) registers. Freescale Semiconductor Functional Description and Application Information ...

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... FIFO. Figure 39 different triggering mechanisms Parameter through Figure 43 show the timing relationship of the master SPI using MC9328MX1 Technical Data, Rev Minimum Maximum Unit 15 – – – – ns – 20 MHz Freescale Semiconductor ...

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... Figure 41. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger SS (input) SCLK, MOSI, MISO Figure 42. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT SS (input) 6 SCLK, MOSI, MISO Figure 43. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge Freescale Semiconductor Functional Description and Application Information MC9328MX1 Technical Data, Rev. 7 ...

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... Tsclk 2 • Tsclk 0 Tsclk + WAIT Figure 44. SPI SCLK Timing Diagram Parameter Minimum 0 100 1 MC9328MX1 Technical Data, Rev. 7 Figure 43 3.0 ± 0.3 V Unit Maximum 1 – – ns – ns – ns – – ns – ns 3.0 ± 0.3 V Unit Maximum 10 MHz – ns Freescale Semiconductor ...

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... Symbol Description T1 End beginning of VSYN T2 HSYN period T3 VSYN pulse width T4 End of VSYN to beginning HSYN pulse width T6 End of HSYN to beginning End beginning of HSYN Freescale Semiconductor Functional Description and Application Information 3.0 ± 0.3 V Minimum – Non-display XMAX T8 (1,1) (1,2) (1,X) T9 T10 Minimum ...

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... MMC/SD module (inner system) and the application (user programming). Bus Clock CMD_DAT Input CMD_DAT Output Figure 47. Chip-Select Read Cycle Timing Diagram 68 Minimum Corresponding Register Value - Valid Data 7 Valid Data 6a MC9328MX1 Technical Data, Rev. 7 Unit Figure 46, all 3 signals 4b 5b Valid Data Valid Data 6b Freescale Semiconductor ...

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... Table 29. Table 29. State Signal Parameters for Card Active Symbol Definition Z High impedance state D Data bits * Repetition CRC Cyclic redundancy check bits (7 bits) Freescale Semiconductor Functional Description and Application Information 1.8 ± 0.1 V Minimum Maximum 0 25 400 6/33 – 15/75 – – ...

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... CRC E Z ****** Content Timing response end to next CMD start (data transfer mode) N cycles CC Host Command CRC ****** Content Timing of command sequences (all modes) until the card sees a stop transmission command. The AC MC9328MX1 Technical Data, Rev and CRC CRC CRC beginning AC Freescale Semiconductor ...

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... CRC status (101); otherwise, a positive CRC status (010) is returned. The card expects a continuous flow of data blocks configured to multiple block mode, with the flow terminated by a stop transmission command. Freescale Semiconductor Functional Description and Application Information N ...

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... Functional Description and Application Information Figure 51. Timing Diagrams at Data Write The stop transmission command may occur when the card is in different states. different scenarios on the bus. 72 MC9328MX1 Technical Data, Rev. 7 Figure 52 shows the Freescale Semiconductor ...

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... Figure 52. Stop Transmission During Different Scenarios Table 30. Timing Values for Parameter MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum (VIL) Command response cycle Identification response cycle Access time delay cycle Freescale Semiconductor Functional Description and Application Information Figure 48 through Symbol Minimum NCR ...

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... Minimum NRC 8 NCC 8 NWR 2 NST 2 S Response IRQ Block Data Interrupt Period Figure 53. SDIO IRQ Timing Diagram MC9328MX1 Technical Data, Rev. 7 (Continued) Maximum Unit – Clock cycles – Clock cycles – Clock cycles 2 Clock cycles ****** IRQ Block Data S E Freescale Semiconductor ...

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... The Memory Stick usually operates in four state access mode and in BS1, BS2, and BS3 bus states. When an error occurs during packet communication, the mode is shifted to two-state access mode, and the BS0 and BS1 bus states are automatically repeated to avoid a bus collision on the SDIO. Freescale Semiconductor Functional Description and Application Information ...

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... MS_SCLKO low pulse width 1 9 MS_SCLKO rise time 1 10 MS_SCLKO fall time 1 11 MS_BS delay time Parameter 1 1 MC9328MX1 Technical Data, Rev 3.0 ± 0.3 V Unit Minimum Maximum – 25 MHz 20 – – ns – – – 25 MHz 20 – – ns – – – Freescale Semiconductor ...

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... Figure 56. PWM Output Timing Diagram Table 32. PWM Output Timing Parameter Table Ref No. Parameter 1 1 System CLK frequency 1 2a Clock high time 1 2b Clock low time 1 3a Clock fall time Freescale Semiconductor Functional Description and Application Information Parameter 1 Table 32 1.8 ± 0.1 V Minimum ...

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... Figure 57. SDRAM Read Cycle Timing Diagram 78 1.8 ± 0.1 V Minimum Maximum Minimum – 6.67 5.7 – 5.7 – COL/ Data Note: CKE is high during the read/write cycle. MC9328MX1 Technical Data, Rev. 7 3.0 ± 0.3 V Unit Maximum – 5/ – – Freescale Semiconductor ...

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... Data out high-impedance time ( Data out high-impedance time ( Active to read/write command period ( SDRAM clock cycle time. This settings can be found in the MC9328MX1 reference manual. RCD Freescale Semiconductor Functional Description and Application Information 1.8 ± 0.1 V Minimum Maximum 2.67 – 6 – 11.4 – ...

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... RP t – RCD2 4.0 – 2.28 – MC9328MX1 Technical Data, Rev. 7 COL/BA 9 DATA 3.0 ± 0.3 V Unit Minimum Maximum 4 – – – – – – ns RP2 t – ns RCD2 2 – – ns Freescale Semiconductor ...

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... Address setup time 5 Address hold time 6 Precharge cycle period 7 Auto precharge command period 1 t and t = SDRAM clock cycle time. These settings can be found in the MC9328MX1 reference manual Freescale Semiconductor Functional Description and Application Information 1.8 ± 0.1 V Minimum Maximum 2.67 – 6 – 11.4 – ...

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... Data moves across the USB in packets. Groups of packets are combined to form data transfers. The same packet transfer mechanism applies to bulk, interrupt, and control transfers. Isochronous data is also moved in the form of packets, however, because isochronous pipes are given a fixed portion of the USB bandwidth at all times, there is no end-of-transfer. 82 MC9328MX1 Technical Data, Rev. 7 Freescale Semiconductor ...

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... ROE_VMO USBD_VPO high to USBD_ROE deactivated VPO_ROE USBD_VMO low to USBD_ROE deactivated (includes SE0) VMO_ROE SE0 interval of EOP FEOPT Data transfer rate PERIOD Freescale Semiconductor Functional Description and Application Information 6 t PERIOD 2 MC9328MX1 Technical Data, Rev VMO_ROE 3 t VPO_ROE t FEOPT 5 3.0 ± 0.3 V ...

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... The I C communication protocol consists of seven elements: START, Data Source/Recipient, Data Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP. SDA SCL Figure 63. Definition of Bus Timing for I 84 Parameter Minimum MC9328MX1 Technical Data, Rev FEOPR 3.0 ± 0.3 V Unit Maximum – Freescale Semiconductor ...

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... STCK Output STFS (bl) Output STFS (wl) Output STXD Output SRXD Input Note: SRXD input in synchronous mode only. Figure 64. SSI Transmitter Internal Clock Timing Diagram Freescale Semiconductor Functional Description and Application Information 2 C Bus Timing Parameter Table 1.8 ± 0.1 V Minimum Maximum 182 – ...

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... SRFS (bl) Output SRFS (wl) Output SRXD Input Figure 65. SSI Receiver Internal Clock Timing Diagram STCK Input STFS (bl) Input STFS (wl) Input STXD Output SRXD Input Note: SRXD Input in Synchronous mode only Figure 66. SSI Transmitter External Clock Timing Diagram MC9328MX1 Technical Data, Rev Freescale Semiconductor ...

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... SRXD setup time before SRCK low 14 SRXD hold time after SRCK low External Clock Operation (Port C Primary Function 1 15 STCK/SRCK clock period 16 STCK/SRCK clock high period 17 STCK/SRCK clock low period Freescale Semiconductor Functional Description and Application Information 1.8 ± 0.1 V Minimum ...

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... Freescale Semiconductor ...

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... STCK high to STFS (wl) low 3 25 SRCK high to SRFS (wl) low 26 STCK high to STXD valid from high impedance 27a STCK high to STXD high 27b STCK high to STXD low Freescale Semiconductor Functional Description and Application Information 1.8 ± 0.1 V Minimum Maximum 1 (Port B Alternate Function 95 – ...

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... Maximum 15.7 26.1 ns 1.0 – – 16.5 – – 1.0 – – ns 3.0V +/- 0.30V Unit Minimum Maximum 2 83.3 – ns 1.5 4.2 ns -0.1 1.0 ns 2.7 4.6 ns 1.1 2.0 ns 1.5 4.2 ns -0.1 1.0 ns 2.7 4.6 ns 1.1 2.0 ns 13.1 14.2 ns 1.1 3.0 ns Freescale Semiconductor ...

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... If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. Freescale Semiconductor Functional Description and Application Information 1 ...

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... The parameters for the timing diagrams are listed in 1 VSYNC HSYNC PIXCLK DATA[7:0] Figure 68. Sensor Output Data on Pixel Clock Falling Edge CSI Latches Data on Pixel Clock Rising Edge 92 Figure Valid Data Valid Data 3 4 MC9328MX1 Technical Data, Rev. 7 shows the timing diagram Table 42. 6 Valid Data Freescale Semiconductor ...

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... For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns. positive duty cycle = 5ns => max rise time allowed = 4ns negative duty cycle = 5ns => max fall time allowed = 4ns Freescale Semiconductor Functional Description and Application Information ...

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... Table 43. Non-Gated Clock Mode Parameters Ref No. 1 csi_vsync to csi_pixclk 2 csi_d setup time 94 Figure Valid Data Valid Data Valid Data Valid Data 2 3 Parameter Min 180 1 MC9328MX1 Technical Data, Rev. 7 shows the timing diagram Table 43 Valid Data 6 4 Valid Data Max Unit – ns – ns Freescale Semiconductor ...

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... Falling-edge latch data max fall time allowed = (negative duty cycle - hold time) max rise time allowed = (positive duty cycle - setup time) Freescale Semiconductor Functional Description and Application Information Parameter Min 1 10.42 10 ...

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... Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX1 Product Family 5 Pin-Out and Package Information Table 44 illustrates the package pin assignments for the 256-pin MAPBGA package ...

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... DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994. 3.MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS. Figure 72. i.MXL 256 MAPBGA Mechanical Drawing Freescale Semiconductor Case Outline 1367 MC9328MX1 Technical Data, Rev. 7 Pin-Out and Package Information ...

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... MC9328MX1 Product Brief (order number MC9328MX1P) MC9328MX1 Reference Manual (order number MC9328MX1RM) The Freescale manuals are available on the Freescale Semiconductors Web site at http://www.freescale.com/imx. These documents may be downloaded directly from the Freescale Web site, or printed versions may be ordered. The ARM Ltd. documentation is available from http://www ...

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... Freescale Semiconductor NOTES MC9328MX1 Technical Data, Rev ...

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... Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use ...