AN2536 Freescale Semiconductor / Motorola, AN2536 Datasheet

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AN2536

Manufacturer Part Number
AN2536
Description
MC9328MX1 and MC9328MXL High Speed Layout Design Guidelines
Manufacturer
Freescale Semiconductor / Motorola
Datasheet

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Application Note
AN2536/D
Rev. 0, 07/2003
MC9328MX1/MXL
HighSpeed Layout
Design Guidelines
Contents
1
2
2.1 Board material effect . . 1
2.2 Noise source and Board
3
3.1 MC9328MX1 ADS 1.1 . 13
3.2 MC9328MX1 Demo 0.1 16
4
5
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice. © Motorola, Inc., 2003. All rights reserved.
design technique . . . . . . 6
Printed Circuit Board. . 19
Introduction . . . . . . . . . 1
Design consideration . . 1
Case Study . . . . . . . . . 13
Design Guidelines on
References . . . . . . . . . 22
1 Introduction
Design of memory systems becomes more complex as the operation frequency increases in a
low power environment. A number of criteria should be considered to achieve maximum
system performance under these conditions. The MC9328MX1/MXL external memory bus
is intended to work with PC100 grade memory. Care must be taken in board layout to
achieve a system capable of maximum bus rates at low voltage.
This document describes the recent investigation into the maximum memory bus frequency
of a low power memory system in terms of stability, capacitive loading, and production
margin. This data will be useful to customers in their design of low-power high speed
memory systems with the i.MX application processors.
2 Design Consideration
To achieve high speed operation in a low power environment, the design of the PCB must
achieve:
2.1 Board Material
Printed Circuit Board (PCB) dielectric construction material controls how much noise and
cross-talk is contributed from the fast switching I/O signals. This dielectric material can be
assigned a dielectric constant (
between two opposite charges separated by a distance in a uniform medium.
Minimal on-board noise generation from the distributed power network
Minimal cross-talk between traces
Reduction of ground bounce effect
Simultaneous switching noise during the operation
Impedance matching by the proper setting on the I/O pad driving strength against the
target memory bus loading
Provide correct signal line termination
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
F = (Q
ε
r
) that is related to the force (see Equation 1) of attraction
1
Q
2
) / (4
πε
r
2
)
Eqn. 1

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AN2536 Summary of contents

Page 1

... Freescale Semiconductor, Inc. Application Note AN2536/D Rev. 0, 07/2003 MC9328MX1/MXL HighSpeed Layout Design Guidelines Contents 1 Introduction 1 Introduction . . . . . . . . . 1 Design of memory systems becomes more complex as the operation frequency increases Design consideration . . 1 2.1 Board material effect . . 1 low power environment. A number of criteria should be considered to achieve maximum 2 ...

Page 2

Freescale Semiconductor, Inc. Design Consideration Where Q and Q are charges distance between the charges (m force (N) and dielectric (F/m). Each PCB substrate has a different relative dielectric constant. The dielectric constant ...

Page 3

Freescale Semiconductor, Inc. Using the typical values mil mil 1.4 mil, microstrip impedance (Z) yields the results show in Figure 2 through Figure 4. The measurement unit in Equation 3 is ...

Page 4

Freescale Semiconductor, Inc. Design Consideration Figure 4. Impedance vs. Trace Thickness (T) Stripline Impedance A circuit trace routed on an inside layer of the PCB with two low-voltage reference planes (i.e., power and / or GND) constitutes a stripline layout. ...

Page 5

Freescale Semiconductor, Inc. Figure 6. Stripline Trace Impedance vs. Trace Height (H) Figure 7. Stripline Trace Impedance vs. Trace Thickness (T) In Figure 5 through Figure 7, we found the impedance is inversely proportional to trace width and directly proportional ...

Page 6

Freescale Semiconductor, Inc. Design Consideration Figure 8. Propagation Delay vs. Dielectric Constant For Microstrip and Stripline Traces. As 2.2 On-Board Noise Source Crosstalk Crosstalk is the unwanted coupling of signals between parallel traces. Proper routing and layer stack-up through microstrip ...

Page 7

Freescale Semiconductor, Inc. • Place a ground plane next to the outer layer to minimize noise. If you use an inner layer to route the clock trace, sandwich the layer between reference planes. • Terminate clock signals to minimize reflection. ...

Page 8

Freescale Semiconductor, Inc. Design Consideration noise is filtered by a large 10-uF capacitor after the ferrite bead. Usually, elements on the PCB add high- frequency noise to the power plane. To filter the high-frequency noise at the device, place decoupling ...

Page 9

Freescale Semiconductor, Inc. • Use ferrite beads to isolate the PLL power supply from digital power supply. Ground Bounce As digital devices become faster, their output switching times decrease. Faster switching times cause higher transient currents in outputs as they ...

Page 10

Freescale Semiconductor, Inc. Design Consideration • Eliminate pull-up resistors or use pull-down resistors. • Use multi-layer PCBs that provide separate VCC and ground planes to utilize the intrinsic capacitance of GND-VCC plane. • Add ohm resistors in ...

Page 11

Freescale Semiconductor, Inc. of the bounce can be large enough to trigger other devices on the PCB. In synchronous designs, ground bounce is less often a problem because synchronous outputs have enough time to settle before the next clock edge. ...

Page 12

Freescale Semiconductor, Inc. Design Consideration Figure 16. Thevenin Parallel Termination Active Parallel Termination—An active parallel termination scheme, the terminating resistor (R tied to a bias voltage ( this scheme, the voltage is selected so that the output drivers ...

Page 13

Freescale Semiconductor, Inc. constant. Therefore, for high-speed designs, you should perform the pre-layout signal integrity simulation with silicon input/output buffer information specification (IBIS) models before using the series termination scheme. 3 MC9328MX1/MXL Case Study The critical high speed signals are ...

Page 14

Freescale Semiconductor, Inc. MC9328MX1/MXL Case Study Figure 21. Recommend Layout of Memory Devices Following is the requirement list we applied to this development board: • Place the 32 kHz and 16 Mhz crystals close to the core and use short ...

Page 15

Freescale Semiconductor, Inc. NET = A2 (The whole trace incl. the route to Socket) COUNTS ------------------------------------------------------------ segments ........... 34 IC drivers ......... 0 IC receivers ....... 7 resistors .......... 0 capacitors ......... 0 INTERCONNECT STATISTICS ------------------------------------ ------- total metal delay ...

Page 16

Freescale Semiconductor, Inc. MC9328MX1/MXL Case Study capacitance no larger than 20pF. With ADS ver 1.1, a standard memory test program is executed (refer to Section 5, “References,” on page 22). It shows smooth execution MHz with a ...

Page 17

Freescale Semiconductor, Inc. Layer Signals Signal Power Signal Signal Signal Signal GND Signal Figure 25. MC9328MX1 Demo v0.1 PCB Layer Description Cap. 6pF 4pF Loading Data Address Signals pin Figure 26. MC9328MX1 Demo v0.1 Device Capacitive Loading Figure 27. MC9328MX1 ...

Page 18

Freescale Semiconductor, Inc. MC9328MX1/MXL Case Study NET = SDCLK INTERCONNECT STATISTICS ------------------------------------------- total metal delay............ 290.740 ps minimum metal Z0 ............. 52.5 ohms maximum metal Z0 ............. 62.5 ohms total metal capacitance ...... 4.7 pF (SDCLK .................................... 4.7 pF) total ...

Page 19

Freescale Semiconductor, Inc. The PCB design were: • 8-layer (refer to Figure 25 on page 17) ε • for FR-4 is 4.1 r • Copper Trace width = 6 mil (rings are not added in the inter-layer of the vias) ...

Page 20

Freescale Semiconductor, Inc. Design Guidelines on PCB • Configure unused I/O pins as output pins, and drive the output low to reduce ground bounce. This configuration will act as a virtual ground. • Configure the unused I/O pins as output, ...

Page 21

Freescale Semiconductor, Inc. • Use multi-layer PCBs that provide separate VCC and ground planes. • Add ohm resistors in series to each of the switching outputs to limit the current flow into each of the outputs. • ...

Page 22

Freescale Semiconductor, Inc. References 5 References 1. Johnson, H.W., and & Graham, M., “High-Speed Digital Design.” Prentice Hall, 1993. 2. Hall, S. H., Hall, G. W., and McCall J. A., “High-Speed Digital System Design.” John Wiley & Sons, Inc. 2000 ...

Page 23

Freescale Semiconductor, Inc. NMOS Fastest Slowest Figure 29. Process Corner Illustration MOTOROLA MC9328MX1/MXL Application Note For More Information On This Product, NOTES PMOS Slowest Fastest Go to: www.freescale.com 23 ...

Page 24

... Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2003 AN2536/D For More Information On This Product, Go to: www.freescale.com ...

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