AN2536 Freescale Semiconductor / Motorola, AN2536 Datasheet - Page 20

• Manufacturer Part Number: AN2536
• Description: MC9328MX1 and MC9328MXL High Speed Layout Design Guidelines
• Manufacturer: Freescale Semiconductor / Motorola

Design Guidelines on PCB
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Configure unused I/O pins as output pins, and drive the output low to reduce ground bounce. This
configuration will act as a virtual ground.
Configure the unused I/O pins as output, and drive high to prevent VCC sag.
Turn on the slow slew rate logic option when speed is not critical.
Eliminate sockets whenever possible.
Depending on the problem, move switching outputs close to either a package ground or VCC pin.
Eliminate pull-up resistors, or use pull-down resistors.
Use multi-layer PCBs that provide separate VCC and ground planes to utilize the intrinsic
capacitance of GND-VCC plane.
Create synchronous designs that are not affected by momentarily switching pins.
Add the recommended de-coupling capacitors to VCC/GND pairs.
Place the decoupling capacitors as close as possible to the power and ground pins of the device.
Connect the capacitor pad to the power and ground plane with larger via to minimize the inductance
in decoupling capacitors and allow for maximum current flow.
Use wide, short traces between the via and capacitor pads, or place the via adjacent to the capacitor
pad.
Traces stretching from power pins to a power plane (or island, or a decoupling capacitor) should be
as wide and as short as possible. This reduces series inductance, and therefore, reduces transient
voltage drops from the power plane to the power pin. Thus, reducing the possibility of ground
bounce.
Use surface-mount low effective series resistance (ESR) capacitors to minimize the lead inductance.
The capacitors should have an ESR value as small as possible.
Connect each ground pin or via to the ground plane individually. A daisy chain connection to the
ground pins shares the ground path, which increases the return current loop and thus inductance.
For equal power distribution, use separate power planes for the analog (PLL) power supply. Avoid
using trace or multiple signal layers to route the PLL power supply.
Use a ground plane next to the PLL power supply plane to reduce power-generated noise.
Place analog and digital components only over their respective ground planes.
Use ferrite beads to isolate the PLL power supply from digital power supply.
Add the recommended decoupling capacitors for as many VCC/GND pairs as possible.
Place the decoupling capacitors as close as possible to the power and ground pins of the device.
Add external buffers at the output of a counter to minimize the loading on silicon device pins.
Configure the unused I/O pin as an output pin and then drive the output low. This configuration acts
as a virtual ground. Connect this low driving output pin to GNDINT and/or the boards ground plane.
Limit load capacitance by buffering loads with an external device, such as the 74244 IC bus driver,
or by reducing the number of devices that drive the bus.
Eliminate sockets whenever possible.
Reduce the number of outputs that can switch simultaneously and/or distribute them evenly
throughout the device.
Move switching outputs close to a package ground pin.
Create a programmable ground next to switching pins.
Eliminate pull-up resistors or use pull-down resistors.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC9328MX1/MXL Application Note
Go to: www.freescale.com
MOTOROLA