AT94K05AL-25AQC Atmel, AT94K05AL-25AQC Datasheet - Page 22

• Manufacturer Part Number: AT94K05AL-25AQC
• Manufacturer: Atmel

Specifications of AT94K05AL-25AQC

• Device System Gates: 5000
• Propagation Delay Time: 12.1ns
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Not Compliant

3.2
Program and Data SRAM
Up to 36 Kbytes of 15 ns dual-port SRAM reside between the FPGA and the AVR. This SRAM is
used by the AVR for program instruction and general-purpose data storage. The AVR is con-
nected to one side of this SRAM; the FPGA is connected to the other side. The port connected
to the FPGA is used to store data without using up bandwidth on the AVR system data bus.
(1)
The FPGA core communicates directly with the data SRAM
block, viewing all SRAM memory
space as 8-bit memory.
Note:
1. The unused bits for the FPGA-SRAM address must tie to ‘0’ because there is no pull-down
circuitry.
For the AT94K10 and AT94K40, the internal program and data SRAM is divided into three
blocks: 10 Kbytes x 16 dedicated program SRAM, 4 Kbytes x 8 dedicated data SRAM and 6
Kbytes x 16 or 12 Kbytes x 8 configurable SRAM, which may be swapped between program and
data memory spaces in 2 Kbytes x 16 or 4 Kbytes x 8 partitions.
For the AT94K05, the internal program and data SRAM is divided into three blocks: 4 Kbytes 16
dedicated program SRAM, 4 Kbytes x 8 dedicated data SRAM and 6 Kbytes x 16 or 12
Kbytes x 8 configurable SRAM, which may be swapped between program and data memory
spaces in 2 Kbytes x 16 or 4 Kbytes x 8 partitions.
The addressing scheme for the configurable SRAM partitions prevents program instructions
from overwriting data words and vice versa. Once configured (SCR41:40 –
See “System Control
Register – FPGA/AVR” on page
30.), the program memory space remains isolated from the data
memory space. SCR41:40 controls internal muxes. Write enable signals allow the memory to be
safely segmented.
Figure 3-2
shows the FPSLIC configurable allocation SRAM memory.
AT94KAL Series FPSLIC
22
1138I–FPSLI–1/08