AT94K05AL-25AQC Atmel, AT94K05AL-25AQC Datasheet - Page 67

• Manufacturer Part Number: AT94K05AL-25AQC
• Manufacturer: Atmel

Specifications of AT94K05AL-25AQC

• Device System Gates: 5000
• Propagation Delay Time: 12.1ns
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Not Compliant

1138I–FPSLI–1/08
• Bit 5 - OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt is executed
if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the
Timer/Counter Interrupt Flag Register – TIFR.
• Bit 4 - TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter2 overflow interrupt is enabled. The corresponding interrupt is executed if an over-
flow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter interrupt flag
register – TIFR.
• Bit 3 - TICIE1: Timer/Counter1 Input Capture Interrupt Enable
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 input capture event interrupt is enabled. The corresponding interrupt is exe-
cuted if a capture-triggering event occurs on pin 29, (IC1), i.e., when the ICF1 bit is set in the
Timer/Counter interrupt flag register – TIFR.
• Bit 2 - OCIE2: Timer/Counter2 Output Compare Interrupt Enable
When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is executed if
a Compare match in Timer/Counter2 occurs, i.e., when the OCF2 bit is set in the Timer/Counter
interrupt flag register – TIFR.
• Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt
Flag Register – TIFR.
• Bit 0 - OCIE0: Timer/Counter0 Output Compare Interrupt Enable
When the OCIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if
a Compare match in Timer/Counter0 occurs, i.e., when the OCF0 bit is set in the Timer/Counter
Interrupt Flag Register – TIFR.
Timer/Counter Interrupt Flag Register – TIFR
• Bit 7 - TOV1: Timer/Counter1 Overflow Flag
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by the hard-
ware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared
by writing a logic 1 to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow
Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In
PWM mode, this bit is set when Timer/Counter1 advances from $0000.
Bit
$38 ($58)
Read/Write
Initial Value
7
TOV1
R/W
0
6
OCF1A
R/W
0
5
OCF1B
R/W
0
4
TOV2
R/W
0
AT94KAL Series FPSLIC
3
ICF1
R/W
0
2
OCF2
R/W
0
1
TOV0
R/W
0
0
OCF0
R/W
0
TIFR
67