AT94K05AL-25AQC Atmel, AT94K05AL-25AQC Datasheet - Page 24

• Manufacturer Part Number: AT94K05AL-25AQC
• Manufacturer: Atmel

Specifications of AT94K05AL-25AQC

• Device System Gates: 5000
• Propagation Delay Time: 12.1ns
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Not Compliant

3.3
3.4
3.4.1
24
Data SRAM Access by FPGA – FPGAFrame Mode
SRAM Access by FPGA/AVR
AT94KAL Series FPSLIC
Accessing and Modifying the Program Memory from the AVR
The FPGA user logic has access to the data SRAM directly through the FPGA side of the dual-
port memory, see
“System Control Register – FPGA/AVR” on page
abled during configuration downloads. Express buses on the East edge of the array are used to
interface the memory. Full read and write access is available. To allow easy implementation, the
interface itself is dedicated in routing resources, and is controlled in the System Designer soft-
ware suite using the AVR FPGA interface dialog.
Figure 3-3.
Once the SCR63 bit is set there is no additional read enable from the FPGA side. This means
that the read is always enabled. You can also perform a read or write from the AVR at the same
time as an FPGA read or write. If there is a possibility of a write address being accessed by both
devices at the same time, the designer should add arbitration to the FPGA Logic to control who
has priority. In most cases the AVR would be used to restrict access by the FPGA using the
FMXOR bit, see
location from both sides simultaneously.
SCR bit 38 controls the polarity of the clock to the SRAM from the AT40K FPGA.
This option is used to allow for code (Program Memory) changes.
The FPSLIC SRAM is up to 36 x 8 Kbytes of dual port, see
Structurally, the [(n • 2) Kbytes 8] memory is built from (n)2 Kbytes 8 blocks, numbered SRAM0
through SRAM(n).
• The A side (port) is accessed by the AVR.
• The B side (port) is accessed by the FPGA/Configuration Logic.
• The B side (port) can be accessed by the AVR with ST and LD instructions in DBG mode for
code self-modify.
FPGA CORE
EMBEDDED
Internal SRAM Access – Normal Use
“Software Control Register – SFTCR” on page
Figure
16 Address Lines:
FPGA Edge Express Buses
8-bit Data Read
8-bit Data Write
CLK FPGA
WE FPGA
3-3. A single bit in the configuration control register (SCR63 – see
SCR38
B Side A Side
16 Kbytes x 8
DATA SRAM
4 Kbytes x 8
UP TO
30) enables this interface. The interface is dis-
16-bit Data Address Bus
8-bit Data Read/Write
Figure
WE AVR
RE AVR
CLK AVR
52. You can read from the same
3-2):
EMBEDDED
AVR CORE
1138I–FPSLI–1/08