MCM20027IBMN Freescale, MCM20027IBMN Datasheet - Page 15

• Manufacturer Part Number: MCM20027IBMN
• Manufacturer: Freescale
• Type: CMOSr

Specifications of MCM20027IBMN

• Sensor Image Color Type: Monochrome
• Sensor Image Size Range: >= 480,000Pixels
• Sensor Image Size: 1280x1024Pixels
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 40C
• Package Type: CLCC
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Revision 8.4 - 24 Oct 2002 :
7.0 Analog Signal Processing Chain Overview
The MCM20027’s analog signal processing (ASP)
chain incorporates Correlated Double Sampling (CDS),
Frame Rate Clamp (FRC), two Digitally Programmable
Gain Amplifiers (DPGA), Offset Correction (DOVA), and
a 10-bit Analog to Digital Converter (ADC).
To see a pictorial depiction of this chain refer to
fications” on page 2
7.1 Correlated Double Sampling (CDS)
The uncertainty associated with the reset action of a ca-
pacitive node results in a reset noise which is equal to
kTC; C being the capacitance of the node, T the temper-
ature and k the Boltzmann constant. A common way of
eliminating this noise source in all image sensors is to
use Correlated Double Sampling. The output signal is
sampled twice, once for its reset (reference) level and
once for the actual video signal. These values are sam-
pled and held while a difference amplifier subtracts the
reference level from the signal output. Double sampling
of the signal eliminates correlated noise sources (see
.“Conceptual block diagram of CDS implementation.”
on page
7.2 Frame Rate Clamp (FRC)
The FRC
ward dark level subtract reference level measurement.
In the automatic FRC mode, the optical black level ref-
erence is re-established each time the image sensor
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Figure 12. Conceptual block diagram of CDS
AVIN
15)
(Figure
13) is designed to provide a feed for-
implementation.
CDSP1
CDSP2
MCM20027
S/H1
S/H2
Freescale Semiconductor, Inc.
For More Information On This Product,
AMP
Go to: www.freescale.com
“Speci-
V+
V-
begins a new frame. The MCM20027 uses optical black
(dark) pixels to aid in establishing this reference.
On the MCM20027, dark pixel input signals should be
sampled for a minimum of 137 s to allow the two 0.1 F
capacitors at the CLRCA and CLRCB pins sufficient
time to charge for 10-bit accuracy. This guarantees that
the FRC’s “droop” will be maintained at <750 V, thus
assuring the specified ADC 10-bit accuracy at +0.5
LSB. Therefore, at maximum operational frequency
(13.5 MHz), the imager would require a number of
frames to establish the dark pixel reference for subse-
quent active pixel processing. The dark pixel sample
period is automatically controlled internally and it is set
to skip the first 3 dark rows and then sample the next 2
dark rows. When “dark clamping” is active, each dark
pixel is processed and held to establish pixel reference
level at the CLRCA and CLRCB pins. During this period,
the FRC’s differential outputs (V+ and V- on the Diff
Amp,
actions help to eliminate the dark level offset, simulta-
neously establishing the desired zero code at the ADC
output.
Care should be exercised in choosing the capacitors for
the CLRCA, B to reflect different frame rates.
The user can disable this function via the
Register; Table 56
Configuration Register, Table 21, on page 41
which will allow the ASP chain to drift in offset Per-Column
Digital Offset Voltage Adjust (DOVA), and controls the
number of rows to clamp on.
Previous
Stage
Figure 13. FRC Conceptual Block Diagram
LRCLMP
LRCLMP
Figure
13) are clamped to V
1X
1X
on page 63 and the
LRCLMP
LRCLMP
-
+
+
-
BUF
BUF
Cap
0.1 f
Cap
0.1 f
V
LRCA
cm
LRCB
ImageMOS
ImageMOS
cm
. Together, these
Diff
Amp
+
-
FRC
Power
FRC Definition
V
V
cm
cm
LRCLMP
LRCLMP
CLRCA
CLRCB
MOTOROLA
V+
V-
15