MC54F283JG ON Semiconductor, MC54F283JG Datasheet - Page 2

• Manufacturer Part Number: MC54F283JG
• Manufacturer: ON Semiconductor

Specifications of MC54F283JG

• Logic Family: F
• Logical Function: Binary Full Adder
• Technology: Bipolar
• Number Of Elements: 1
• Number Of Bits: 4
• Propagation Delay Time: 14ns
• High Level Output Current: -1mA
• Low Level Output Current: 20mA
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -55C to 125C
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Pin Count: 16
• Mounting: Through Hole
• Operating Temperature Classification: Military
• Lead Free Status / RoHS Status: Compliant

4-BIT BINARY FULL ADDER
(With Fast Carry)
lookahead, accepts two 4-bit binary words (A 0 –A 3 , B 0 –B 3 ) and a Carry input
(C 0 ). It generates the binary Sum outputs (S 0 –S 3 ) and the Carry output (C 4 )
from the most significant bit. The F283 will operate with either active-HIGH or
active-LOW operands (positive or negative logic).
The binary sum appears on the Sum (S 0 –S 3 ) and outgoing carry (C 4 ) outputs.
The binary weight of the various inputs and outputs is indicated by the sub-
script numbers, representing powers of two.
A 0 , B 0 can be arbitrarily assigned to pins 5, 6 and 7. Due to the symmetry of
the binary add function, the F283 can be used either with all inputs and outputs
active HIGH (positive logic) or with all inputs and outputs active LOW (nega-
tive logic). See Figure A. Note that if C 0 is not used it must be tied LOW for
active-HIGH logic or tied HIGH for active-LOW logic.
out for use as inputs or outputs. However, other means can be used to effec-
tively insert a carry into, or bring a carry out from, an intermediate stage. Fig-
ure B shows how to make a 3-bit adder. Tying the operand inputs of the fourth
adder (A 3 , B 3 ) LOW makes S 3 dependent only on, and equal to, the carry from
the third adder. Using somewhat the same principle, Figure C shows a way
of dividing the F283 into a 2-bit and a 1-bit adder. The third stage adder (A 2 ,
B 2 , S 2 ) is used merely as a means of getting a carry (C 10 ) signal into the fourth
stage (via A 2 and B 2 ) and bringing out the carry from the second stage on S 2 .
Note that as long as A 2 and B 2 are the same, whether HIGH or LOW, they do
not influence S 2 . Similarly, when A 2 and B 2 are the same the carry into the third
stage does not influence the carry out of the third stage. Figure D shows a
method of implementing a 5-input encoder, where the inputs are equally
weighted. The outputs S 0 , S 1 and S 2 present a binary number equal to the
number of inputs I 1 –I 5 that are true. Figure E shows one method of implement-
ing a 5-input majority gate. When three or more of the inputs I 1 –I 5 are true, the
output M 5 is true.
The MC54/74F283 high-speed 4-bit binary full adder with internal carry
The F283 adds two 4-bit binary words (A plus B) plus the incoming carry C 0 .
2 0 (A 0 + B 0 + C 0 ) + 2 1 (A 1 + B 1 ) + 2 2 (A 2 + B 2 ) + 2 3 (A 3 + B 3 )
= S 0 + 2S 1 + 4S 2 + 8S 3 + 16C 4
Where (+) = plus
Interchanging inputs of equal weight does not affect the operation.Thus C 0 ,
Due to pin limitations, the intermediate carries of the F283 are not brought
V CC
S 1
16
1
B 2
15
B 1
2
CONNECTION DIAGRAM
A 2
14
A 1
3
S 2
13
S 0
4
A 3
12
A 0
5
B 3
11
B 0
6
FUNCTIONAL DESCRIPTION
FAST AND LS TTL DATA
S 3
10
C 0
7
GND
C 4
9
8
4-146
16
16
4-BIT BINARY FULL ADDER
MC54/74F283
ORDERING INFORMATION
16
1
1
FAST
MC54FXXXJ
MC74FXXXN
MC74FXXXD
13
10
4
1
(With Fast Carry)
1
LOGIC SYMBOL
S 0
S 1
S 2
S 3
SCHOTTKY TTL
C 0
C 4
7
9
Ceramic
Plastic
SOIC
A 0
B 0
A 1
B 1
A 2
B 2
A 3
B 3
CASE 751B-03
CASE 620-09
CASE 648-08
CERAMIC
N SUFFIX
D SUFFIX
J SUFFIX
PLASTIC
V CC = PIN 16
GND = PIN 8
SOIC
5
6
3
2
14
15
12
11