MC54-74HC365 MOTOROLA [Motorola, Inc], MC54-74HC365 Datasheet

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MC54-74HC365

Manufacturer Part Number
MC54-74HC365
Description
Hex 3-State Noninverting Buffer with Common Enables
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex 3-State Noninverting
Buffer with Common Enables
High–Performance Silicon–Gate CMOS
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
common active–low Output Enables. When either of the enables is high, the
buffer outputs are placed into high–impedance states. The HC365 has
noninverting outputs.
10/95
Motorola, Inc. 1995
The MC54/74HC365 is identical in pinout to the LS365. The device inputs
This device is a high–speed hex buffer with 3–state outputs and two
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 90 FETs or 22.5 Equivalent Gates
OUTPUT ENABLE 1
OUTPUT ENABLE 2
LOGIC DIAGRAM
15
1
A0
A1
A2
A3
A4
A5
2
4
6
10
12
14
PIN 16 = V CC
PIN 8 = GND
3
5
7
11
13
9
Y0
Y1
Y2
Y3
Y4
Y5
1
REV 6
16
16
MC54/74HC365
16
X = don’t care
Z = high impedance
Enable
ENABLE 1
1
1
OUTPUT
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXDT
H
X
1
L
L
ORDERING INFORMATION
1
GND
A0
Y0
A1
Y1
A2
Y2
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
Enable
1
2
3
4
5
6
7
8
X
H
2
L
L
CERAMIC PACKAGE
PLASTIC PACKAGE
TSSOP PACKAGE
CASE 948F–01
CASE 620–10
CASE 648–08
16
15
14
13
12
10
11
A
H
X
X
L
DT SUFFIX
9
N SUFFIX
J SUFFIX
Ceramic
Plastic
TSSOP
V CC
OUTPUT
ENABLE 2
A5
Y5
A4
Y4
A3
Y3
Output
H
Y
L
Z
Z

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MC54-74HC365 Summary of contents

Page 1

... Hex 3-State Noninverting Buffer with Common Enables High–Performance Silicon–Gate CMOS The MC54/74HC365 is identical in pinout to the LS365. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device is a high–speed hex buffer with 3–state outputs and two common active– ...

Page 2

... MC54/74HC365 Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 3

... V CC GND t PHL OUTPUT Y OUTPUT Y t THL 3 MC54/74HC365 Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 4

... MC54/74HC365 TEST POINT OUTPUT DEVICE UNDER TEST * Includes all probe and jig capacitance Figure 3. INPUT A OUTPUT ENABLE 1 OUTPUT ENABLE 2 MOTOROLA TEST CIRCUITS OUTPUT DEVICE UNDER TEST * Includes all probe and jig capacitance LOGIC DETAIL TO OTHERS FIVE BUFFERS 4 TEST POINT CONNECT WHEN 1 k TESTING t PLZ AND t PZL ...

Page 5

... SEATING –T PLANE – MC54/74HC365 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MILLIMETERS DIM ...

Page 6

... D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 –W– K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC MC54/74HC365/D High–Speed CMOS Logic Data DL129 — Rev 6 ...

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