MC54-74HC374A MOTOROLA [Motorola, Inc], MC54-74HC374A Datasheet

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MC54-74HC374A

Manufacturer Part Number
MC54-74HC374A
Description
Octal 3-State Non-Inverting D Flip-Flop
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
Octal 3-State
Non-Inverting D Flip-Flop
High–Performance Silicon–Gate CMOS
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
of the clock. The Output Enable input does not affect the states of the
flip–flops, but when Output Enable is high, the outputs are forced to the
high–impedance state; thus, data may be stored even when the outputs are
not enabled.
pins on the opposite side of the package from the output. This device is
similar in function to the HC534A which has inverting outputs.
8/96
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1996
The MC54/74HC374A is identical in pinout to the LS374. The device
Data meeting the setup time is clocked to the outputs with the rising edge
The HC374A is identical in function to the HC574A which has the input
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 266 FETs or 66.5 Equivalent Gates
OUTPUT ENABLE
INPUTS
DATA
CLOCK
D0
D1
D2
D3
D4
D5
D6
D7
X = don’t care
Z = high impedance
Output
Enable
H
L
L
L
3
4
7
8
13
14
17
18
11
1
FUNCTION TABLE
LOGIC DIAGRAM
Inputs
Clock
L,H,
X
D
H
X
X
L
3–1
No Change
Output
12
15
16
19
2
5
6
9
PIN 20 = V CC
PIN 10 = GND
Q
H
Z
L
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
NONINVERTING
OUTPUTS
REV 7
MC54/74HC374A
20
20
20
20
20
1
OUTPUT
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
MC74HCXXXASD
MC74HCXXXADT
ENABLE
1
ORDERING INFORMATION
GND
1
1
Q1
1
Q0
D1
Q2
Q3
D0
D2
D3
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
CERAMIC PACKAGE
PLASTIC PACKAGE
TSSOP PACKAGE
SSOP PACKAGE
SOIC PACKAGE
CASE 751D–04
CASE 940C–03
CASE 948E–02
20
19
18
17
16
15
14
13
12
11
CASE 732–03
CASE 738–03
DW SUFFIX
SD SUFFIX
DT SUFFIX
N SUFFIX
J SUFFIX
Ceramic
Plastic
SOIC
SSOP
TSSOP
V CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CLOCK

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MC54-74HC374A Summary of contents

Page 1

... Octal 3-State Non-Inverting D Flip-Flop High–Performance Silicon–Gate CMOS The MC54/74HC374A is identical in pinout to the LS374. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Data meeting the setup time is clocked to the outputs with the rising edge of the clock. The Output Enable input does not affect the states of the flip– ...

Page 2

... MC54/74HC374A Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î MAXIMUM RATINGS* Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 3

... 3–3 MC54/74HC374A Î Î Î Î Î Î Î Î Î Î Î Î Guaranteed Limit Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 4

... MC54/74HC374A Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î TIMING REQUIREMENTS ( pF, Input 6.0 ns) Î ...

Page 5

... 3–5 MC54/74HC374A TEST POINT CONNECT WHEN 1 k TESTING t PLZ AND t PZL . CONNECT TO GND WHEN TESTING t PHZ AND t PZH . Figure ...

Page 6

... MC54/74HC374A SEATING PLANE –A– –T– SEATING PLANE –A– –B– 20X 0.010 (0.25 18X K MOTOROLA OUTLINE DIMENSIONS J SUFFIX CERAMIC PACKAGE CASE 732–03 ISSUE ...

Page 7

... DETAIL DETAIL E 3–7 MC54/74HC374A NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION ...

Page 8

... MC54/74HC374A Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...

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