74HCT7030D-T NXP Semiconductors, 74HCT7030D-T Datasheet - Page 19
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74HCT7030D-T
Manufacturer Part Number
74HCT7030D-T
Description
Manufacturer
NXP Semiconductors
Datasheet
1.74HCT7030D-T.pdf
(22 pages)
Specifications of 74HCT7030D-T
Logic Family
HCT
Logical Function
FIFO Register
Number Of Elements
1
Number Of Bits
9
Number Of Inputs
9
Number Of Outputs
9
High Level Output Current
-6mA
Low Level Output Current
6mA
Package Type
SO
Propagation Delay Time
117ns
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Polarity
Non-Inverting
Technology
CMOS
Frequency (max)
36(Typ)MHz
Mounting
Surface Mount
Pin Count
28
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Quiescent Current
50uA
Output Type
3-State
Lead Free Status / RoHS Status
Compliant
Philips Semiconductors
December 1990
9-bit x 64-word FIFO register; 3-state
(1) HC : V
Fig.20 FIFO to FIFO communication; input timing under empty condition.
HCT: V
M
M
= 50%; V
= 1.3 V; V
I
I
= GND to V
= GND to 3 V.
CC
.
19
Notes to Fig.20
1. FIFO
2. Load one word into FIFO
3. Data out
4. DOR
5. DIR
6. DIR
7. DOR
SO
data.
pulse applied, results in DIR
pulse.
valid data arrives at FIFO
stage after a specified delay of
the DOR flag, meeting data input
set-up requirements of FIFO
(ripple through delay after
SI
FIFO
output ready pulse, data is shifted
into FIFO
indicates input stage of FIFO
busy, shift-out of FIFO
complete.
automatically; the input stage of
FIFO
data, SO is held HIGH in
anticipation of additional data.
delay after SI
present one propagation delay
later at the FIFO
A
A
LOW) data is unloaded from
B
B
held HIGH in anticipation of
A
B
A
A
B
and SO
and SO
74HC/HCT7030
and SI
goes HIGH; (ripple through
and FIFO
as a result of the data
is again able to receive
A
B
/data in
.
Product specification
B
B
A
A
LOW) valid data is
pulse HIGH;
go LOW; flag
go HIGH
B
B
initially empty,
output stage.
B
transition;
A
is
A
A
; SI
output
B
B
.
is