74HCT7030D-T NXP Semiconductors, 74HCT7030D-T Datasheet - Page 20
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74HCT7030D-T
Manufacturer Part Number
74HCT7030D-T
Description
Manufacturer
NXP Semiconductors
Datasheet
1.74HCT7030D-T.pdf
(22 pages)
Specifications of 74HCT7030D-T
Logic Family
HCT
Logical Function
FIFO Register
Number Of Elements
1
Number Of Bits
9
Number Of Inputs
9
Number Of Outputs
9
High Level Output Current
-6mA
Low Level Output Current
6mA
Package Type
SO
Propagation Delay Time
117ns
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Polarity
Non-Inverting
Technology
CMOS
Frequency (max)
36(Typ)MHz
Mounting
Surface Mount
Pin Count
28
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Quiescent Current
50uA
Output Type
3-State
Lead Free Status / RoHS Status
Compliant
Philips Semiconductors
December 1990
9-bit x 64-word FIFO register; 3-state
(1) HC : V
Fig.21 FIFO to FIFO communication; output timing under full condition.
HCT: V
M
M
= 50%; V
= 1.3 V; V
I
I
= GND to V
= GND to 3 V.
CC
.
20
Notes to Fig.21
1. FIFO
2. Unload one word from FIFO
3. DIR
4. DOR
5. DOR
6. DIR
SI
shifting in new data as empty
location bubbles-up.
SO pulse applied, results in DOR
pulse.
(bubble-up delay after SO
data is loaded into FIFO
result of the DIR pulse, data is
shifted out of FIFO
indicates the output stage of
FIFO
complete.
indicates valid data is again
available at FIFO
SI
bubble-up of empty location.
delay after SO
location is present at input stage
of FIFO
B
B
held HIGH in anticipation of
B
is held HIGH, awaiting
A
A
A
A
A
and SO
goes HIGH; (bubble-up
74HC/HCT7030
and SI
and SI
and FIFO
is busy, shift-in to FIFO
A
.
Product specification
A
B
B
A
pulse HIGH;
go LOW; flag
go HIGH; flag
LOW) an empty
B
A
initially full,
A
output stage,
.
B
B
as a
LOW)
B
;
B
is