CY7C4281V-10JC Cypress Semiconductor Corp, CY7C4281V-10JC Datasheet
CY7C4281V-10JC
Specifications of CY7C4281V-10JC
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CY7C4281V-10JC Summary of contents
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... CY7C4281V/CY7C4291V CY7C4261V/CY7C4271V16K/32K/64K/128K x 9 Low-Voltage Deep Sync™ FIFOs 16K/32K/64K/128K x 9 Low-Voltage Deep Sync™ FIFOs Features • 3.3V operation for low power consumption and easy integration into low-voltage systems • High-speed, low-power, first-in first-out (FIFO) memories • 16K × 9 (CY7C4261V) • 32K × 9 (CY7C4271V) • ...
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... Resets device to empty condition. A reset is required before an initial read or write operation after power-up. When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected HIGH, the FIFO’s outputs are in High Z (high-impedance) state. CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V 7C4261/71/81/91V-25 Unit 40 MHz ...
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... WEN2/LD and WEN1 are LOW. The fifth LOW-to-HIGH transition of WCLK while WEN2/LD and WEN1 are LOW writes data to the empty LSB register again. Figure 1 shows before ENS the registers sizes and default values for the various device types. 0–8 CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V outputs 0-8 outputs 0-8 Page [+] Feedback ...
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... LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW when the number of unread words in the FIFO is greater than or equal to CY7C4261V (16k – m), CY7C4271V (32k – m), CY7C4281V (64k – m) and CY7C4291V (128k – m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of available memory locations is greater than m ...
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... The Empty Flag (EF) will go LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regardless of the state of REN1 and REN2 synchronized to RCLK, i.e exclusively updated by each rising edge of RCLK. RESET (RS) 9 CY7C4261V CY7C4271V CY7C4281V CY7C4291V Read Enable 2 (REN2) Used in a Width-Expansion Configuration CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V CY7C4291V FF PAF PAE [ [3] ...
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... Com’l 4 Ind Test Conditions ° MHz 3.3V CC [8, 9] 3.0V R2=510Ω GND ≤ 2.0V . CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V + 0.5V CC [4] Ambient Temperature V CC 3.3V ±300 mV 0°C to +70°C −40°C to +85°C 3.3V ±300 mV 7C4261/71/81/91V Min. Max. Min. Max. Unit 2.4 2 ...
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... Pulse widths less than minimum values are not allowed. 11. Values guaranteed by design, not currently tested. Document #: 38-06013 Rev. *B (-10) (continued) All Input Pulses 3.0V 10% GND ≤ 7C4261/71/81/91V- 7C4261/71/81/91V- 10 Min. Max. Min. 100 4.5 4.5 3 [11 [11 CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V 90% 90% 10% ≤ 7C4261/71/81/91V Max. Min. Max. Unit 66.7 40 MHz ...
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... CKL t CLKL NO OPERATION t REF VALID DATA [13] SKEW1 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V NO OPERATION NO OPERATION t WFF REF t OHZ Page [+] Feedback ...
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... Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable flag offset registers. Document #: 38-06013 Rev RSS RSR t t RSR RSS t t RSS RSR t RSF t RSF t RSF CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V [15 OE=0 Page [+] Feedback ...
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... REN2 Q – Notes: 17. When t > minimum specification, t (maximum SKEW1 FRL + t . The Latency Timing applies only at the Empty Boundary (EF = LOW). SKEW1 18. The first word is available the cycle after EF goes HIGH, always. Document #: 38-06013 Rev. *B CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V [17] t FRL t REF OLZ When t < minimum specification, t ...
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... ENH ENS WEN1 t t ENS ENH WEN2 (if applicable) [17] t FRL RCLK t SKEW1 EF REN1, REN2 LOW OE DATA IN OUTPUT REGISTER Q – Document #: 38-06013 Rev. *B CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V t DS DATA WRITE 2 t ENS t ENS REF REF SKEW1 ENH t ENH [17] t FRL t REF DATA READ Page ...
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... If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW. Document #: 38-06013 Rev SKEW1 DATA WRITE t WFF DATA READ t CLKL t ENS ENH Note 20 t ENS ENH t [19] PAE t ENS CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V NO WRITE [12] DATA WRITE t WFF t ENH t ENS t A NEXT DATA READ WORDS Note21 IN FIFO t PAE t t ENS ENH Page [+] Feedback ...
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... If a write is performed on this rising edge of the write clock, there will be Full − (m−1) words of the FIFO when PAF goes LOW. 23. PAF offset = m. 24. 16K − m words for CY7C4261V, 32K – m words for CY7C4271V, 64K − m words for CY7C4281V, and 128K − m words for CY4291V. 25 the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle ...
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... Low-voltage Deep Sync FIFO Speed (ns) Ordering Code Package Name 10 CY7C4271V-10JC CY7C4271V-10JXC 15 CY7C4271V-15JC CY7C4271V-15JI 25 CY7C4271V-25JC 64kx9 Low-voltage Deep Sync FIFO Speed (ns) Ordering Code Package Name 10 CY7C4281V-10JC CY7C4281V-10JXC 15 CY7C4281V-15JC CY7C4281V-15JI 25 CY7C4281V-25JC 128kx9 Low-voltage Deep Sync FIFO Speed (ns) Ordering Code Package Name 10 CY7C4291V-10JC CY7C4291V-10JXC 15 CY7C4291V-15JC CY7C4291V-15JXC ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 32-Lead Plastic Leaded Chip Carrier J65 CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V 51-85002-*B Page [+] Feedback ...
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... Document History Page Document Title: CY7C4261V/CY7C4271V/CY7C4281V/CY7C4291V 16K/32K/64K/128K/X9 Low-Voltage Deep Sync FIFO Document Number: 38-06013 Orig. of REV. ECN NO. Issue Date Change ** 106474 09/15/01 SZV *A 127858 09/04/03 FSG *B 386127 See ECN ESH Document #: 38-06013 Rev. *B CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Description of Change Changed Spec number from 38-00656 to 38-06013 ...