AD6622AS Analog Devices Inc, AD6622AS Datasheet - Page 18

• Manufacturer Part Number: AD6622AS
• Manufacturer: Analog Devices Inc

Specifications of AD6622AS

• Lead Free Status / RoHS Status: Not Compliant

AD6622
Start refers to the start-up of an individual channel, chip, or
multiple chips. If a channel is not used, it should be put in the
Sleep Mode to reduce power dissipation. Following a hard reset
(low pulse on the AD6622 RESET pin), all channels are placed
in the Sleep Mode.
Start with No Sync
If no synchronization is needed to start multiple channels or
multiple AD6622s, the following method can be used to ini-
tialize the device.
1. To program a channel, it must first be set to the Program
2. Set the appropriate program and sleep bits low (External
Start with Soft Sync
The AD6622 includes the ability to synchronize channels or chips
under microprocessor control. One action to synchronize is the
start of channels or chips. The Start Update Hold-Off Counter
(0x00) in conjunction with the start bit and sync bit (External
Address 5) allow this synchronization. Basically the Start Update
Mode (bit high) and Sleep Mode (bit high) (External Address
4). The Program Mode allows programming of data memory
and coefficient memory (all other registers are programmable
whether or not in Program Mode). Since no synchronization
is used all sync bits are set low (External Address 5). All
appropriate control and memory registers (filter) are then
loaded. The Start Update Hold-Off Counter (0x00) should
be set to 0.
Address 4). This enables the channel. The channel must have
Program and Sleep Mode low to activate a channel.
HOP SYNC
START SYNC
ADDRESS 4
EXTERNAL
32
16
16
FREQUENCY
REGISTER
HOLD-OFF
HOLD-OFF
D
D
D
START
NCO
HOP
Q
Q
Q
16
16
32
CLK
REGISTER
HOLD-OFF
COUNTER
COUNTER
D
PL
D
PL
D
START
NCO
ENA
C = 0
C = 0
C = 1
C = 1
ENA
ENA
Q
ACCUMULATOR
32
NCO PHASE
RESET
SET
D
PIN
Q
SLEEP
Hold-Off Counter delays the start of a channel(s) by its value
(number of AD6622 CLKs). The following method is used to
synchronize the start of multiple channels via microprocessor
control.
1. Set the appropriate channels to sleep mode (a hard reset
2. Write the Start Update Hold-Off Counter(s) (0x00) to the
3. Write the Start bit and the SyncX(s) bit high (External
4. This starts the Start Update Hold-Off Counter counting
Start with Pin Sync
A sync pin is provided on the AD6622 to provide the most
accurate synchronization, especially between multiple AD6622s.
Synchronization of start with an external signal is accomplished
with the following method.
1. Set the appropriate channels to sleep mode (a hard reset to
2. Write the Start Update Hold-Off Counter(s) (0x00) to the
3. Set the start on pin sync bit and the appropriate sync pin
4. When the sync pin is sampled high by the AD6622 CLK, it
Hop is a jump from one NCO frequency to a new NCO frequency.
This change in frequency can be synchronized via microproces-
sor control or an external sync signal as described below.
To set the NCO frequency without synchronization the follow-
ing method should be used.
Set Freq No Hop
1. Set the NCO Freq Hold-Off Counter to 0.
2. Load the appropriate NCO frequency. The new frequency
Hop with Soft Sync
The AD6622 includes the ability to synchronize a change in
NCO frequency of multiple channels or chips under micro-
processor control. The NCO Freq Hold-Off Counter (0x03), in
conjunction with the hop bit and the sync bit (Ext Address 5),
allow this synchronization. Basically the NCO Freq Hold-Off
Counter delays the new frequency from being loaded into the
NCO by its value (number of AD6622 CLKs). The following
method is used to synchronize a hop in frequency of multiple chan-
nels via microprocessor control.
to the AD6622 RESET pin brings all four channels up in
sleep mode).
appropriate value (greater than 1 and less than 2
chip(s) is not initialized, all other registers should be loaded
at this step.
Address 5).
down. The counter is clocked with the AD6622 CLK signal.
When it reaches a count of one the Sleep bit of the appropri-
ate channel(s) is set low to activate the channel(s).
the AD6622 RESET pin brings all four channels up in
sleep mode).
appropriate value (greater than 1 and less than 2
chip(s) is not initialized, all other registers should be loaded
at this step.
enable high (0x001).
enables the countdown of the Start Update Hold-Off Counter.
The counter is clocked with the AD6622 CLK signal. When
it reaches a count of one, the sleep bit of the appropriate
channel(s) is set low to activate the channel(s).
will immediately be loaded to the NCO.
16
16
–1). If the
–1). If the