AD6622AS Analog Devices Inc, AD6622AS Datasheet - Page 24

• Manufacturer Part Number: AD6622AS
• Manufacturer: Analog Devices Inc

Specifications of AD6622AS

• Lead Free Status / RoHS Status: Not Compliant

AD6622
(0x000) Summation Mode Control
Controls functions in the summation block of the AD6622. When
set high, Bit 0 causes the output data to be clipped (no wrap-
around) when overrange of the output occurs. When Bit 0 is low,
overrange will result in wraparound. When set low, Bit 1 formats
the output data as two's complement. Bit 1 set high will for-
mat output data as offset binary.
(0x001) Sync Mode Control
Bits 3–0 when high enable synchronization of these channels.
See the Synchronization section of the data sheet for detailed
explanation.
Channel Function Registers
The following registers are channel-specific. “0x” denotes that
these values are represented as hexadecimal numbers. “n” repre-
sents the specified channel. Valid channels are n = 1, 2, 3, and 4.
(0xn00) Start Update Hold-Off Counter
The Start Update Hold-Off Counter is used to synchronize start
up of AD6622 channels and can be used to synchronize multiple
chips. The Start Update Hold-Off Counter is clocked by the
AD6622 CLK (master clock). See the Synchronization section
of the data sheet for detailed explanation. If no synchronization
is required, this register should be set to 0.
(0xn01) NCO Control
Bit 1:0 set the NCO scaling per the Table XIV.
0x01 Bit 1
0
0
1
1
Bit 2, when high, clears the NCO phase accumulator to 0 on
either a Soft Sync or Pin Sync (see Synchronization for details).
Bit 3, when high, enables NCO phase dither.
Bit 4, when high, enables NCO amplitude dither.
Bits 7:5 are reserved and should be written low.
(0xn02) NCO Frequency
This register is a 32-bit unsigned integer that sets the NCO
Frequency. The NCO Frequency contains a shadow register for
synchronization purposes. The shadow can be read back directly,
the NCO Frequency cannot.
(0xn03) NCO Frequency Update Hold-Off Counter
The Hold-Off Counter is used to synchronize the change of
NCO frequencies. See the Synchronization section of the data
sheet for detailed explanation. If no synchronization is required,
this register should be set to 0.
(0xn04) NCO Phase Offset
This register is a 16-bit unsigned integer that is added to the phase
accumulator of the NCO. This allows phase synchronization of
multiple channels of the AD6622(s). See the Synchronization
section of the data sheet for details. The NCO Phase Offset con-
tains a shadow register for synchronization purposes. The shadow
can be read back directly, the NCO Phase Offset cannot.
NCO
Frequency
=
Table XIV. Control Scale
0x01 Bit 0
0
1
0
1
2
32
×



CLK
f
channel



NCO Output Level
–6 dB
–12 dB
–18 dB
–24 dB
(20)
(0xn05) NCO Phase Offset Update Hold-Off Counter
The Hold-Off Counter is used to synchronize the change of NCO
phases. See the Synchronization section of the data sheet for
detailed explanation. If no synchronization is required, this
register should be set to 0.
(0xn06) CIC Scale
Bits 5:0 set the CIC scaling per the equation below.
See CIC section of the data sheet for details. Bits 7:6 are reserved
and should be set to 0.
(0xn07) Reserved
This register is reserved and should be set to 0.
(0xn08) CIC2 Interpolation – 1
This register sets the interpolation rate for the CIC2 filter stage
(unsigned integer). The programmed value is the CIC2 Interpo-
lation – 1. Maximum interpolation is limited by the CIC scaling
available (See CIC section of the data sheet).
(0xn09) CIC5 Interpolation – 1
This register sets the interpolation rate for the CIC5 filter
stage (unsigned integer). The programmed value is the CIC5
Interpolation – 1. Maximum interpolation is limited by the CIC
scaling available (See CIC section of the data sheet).
(0xn0A) Number of RCF Coefficients – 1
This register sets the number of RCF Coefficients and is limited
to a maximum of 128. The programmed value is the number of
RCF Coefficients – 1.
(0xn0B) RCF Coefficient Offset
This register sets the offset for RCF Coefficients and is normally
set to 0. It can be viewed as a pointer that selects the portion of
the CMEM used when computing the RCF filter. This allows
multiple filters to be stored in the coefficient memory space,
selecting the appropriate filter by setting the offset.
(0xn0C) Channel Mode Control 1
Bits 3:0 set N
Bits 5:4 set the channel input format as shown below.
Bit 6 Reserved.
Bit 7 Reserved.
(0xn0D) Channel Mode Control 2
Bits 4:0 set the SCLK
frequency based on the following equation.
CIC Scale
f
SCLK
Bit 5
0
0
1
1
_
=
RCF
2
×
/L
=
(
SCLK
ceil
RCF
Table XV. Filter Mode
DIVIDER
CLK
-1.
(log (
DIVIDER
Bit 4
0
1
0
1
2
L
which determines the serial clock
CIC
+
5
4
1
)
×
L
CIC
Input Mode
FIR
Reserved
Reserved
Reserved
2
))
(21)
(22)