W83195BR-341-TR Nuvoton Technology Corporation of America, W83195BR-341-TR Datasheet
W83195BR-341-TR
Specifications of W83195BR-341-TR
Related parts for W83195BR-341-TR
W83195BR-341-TR Summary of contents
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... W83195BR-341 W83195BG-341 WINBOND CLOCK GENERATOR FOR VIA P4/KT SERIES CHIPSET Date: Mar/21/2006 Revision: 1.1 ...
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... CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET W83195BR-341/W83195BG-341 Data Sheet Revision History PAGES DATES VERSION 1 2 n.a. 07/07/03 3 n.a. 26/8/ 12/18/03 5 05/03/04 6 03/21/ Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners ...
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CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET Table of Content- 1. GENERAL DESCRIPTION ......................................................................................................... 1 2. PRODUCT FEATURES .............................................................................................................. 1 3. PIN CONFIGURATION ............................................................................................................... 2 4. BLOCK DIAGRAM ...................................................................................................................... 2 5. PIN DESCRIPTION..................................................................................................................... 3 5.1 Crystal I/O.................................................................................................................................3 5.2 CPU, AGP, ...
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CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET 8. ACCESS INTERFACE .............................................................................................................. 16 8.1 Block Write protocol ...............................................................................................................16 8.2 Block Read protocol ...............................................................................................................16 8.3 Byte Write protocol .................................................................................................................16 8.4 Byte Read protocol.................................................................................................................16 9. SPECIFICATIONS .................................................................................................................... 17 9.1 ABSOLUTE MAXIMUM RATINGS .......................................................................................17 ...
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... S.S.T. scale to reduce EMI. The W83195BR-341 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. 2. PRODUCT FEATURES • 1 pairs differential clock for CPU (P4 or Athlon) • ...
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CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET 3. PIN CONFIGURATION ...
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CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET 5. PIN DESCRIPTION BUFFER TYPE SYMBOL IN Input IN Latch input pin and internal 120KΩ pull down td120k IN Latch input pin and internal 120KΩ pull up tp120k OUT Output OD Open Drain ...
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CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET CPU, AGP, PCI Clock Outputs, continued PIN PIN NAME 8 AGP2 PCI_STOP#* 10 PCI_F & FS1 11 PCI1 & SELSD_DD 12 PCI2 MULTSEL* 14, 15, 17, PCI [3:6] 18 5.3 Fixed Frequency Outputs ...
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CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET 5.4 DRAM Buffer PIN PIN NAME 45 BUF_IN 46 FBOUT 44,42,38,36,32 DDRT[0:5] ,30 SDRAM [0,2,4,6,8,10] 43,41,37,35,31 DDRC[0:5] ,29 SDRAM [1,3,5,7,9,11] 5.5 I2C Control Interface PIN PIN NAME 28 SDATA* 27 SCLK* 5.6 Output ...
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CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET 5.7 Power an GND Pins PIN PIN NAME 5 VDDAGP 16 VDDPCI 22 VDD48 23 34, 2,9,13,19,24,33,39,47,54 TYPE PWR 3.3V power supply for AGP. PWR 3.3V power supply for PCI. ...
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CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET 6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE This frequency table is used at power on latched FS [4:0] value or software programming at SSEL [4:0] (Register 0 bit 7 ~ 3). FS4 FS3 ...
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CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET 7. I2C CONTROL AND STATUS REGISTERS (The register No. Is increased use byte data read/write protocol) 7.1 Register 0: Frequency Select (Default =08h) BIT NAME PWD 7 SSEL [4] 0 ...
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CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET 7.3 Register 2: PCI Clock (1 = Enable Disable) (Default: FEh) BIT NAME PWD 7 PCI_F 1 6 PCI6 1 5 PCI5 1 4 PCI4 1 3 PCI3 1 2 PCI2 ...
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CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET 7.7 Register 7: M/N Program (Default: 2Fh) BIT NAME PWD 7 N_DIV [ N_DIV [ N_DIV [5] 1 Programmable N divisor value bit 7 ~0. 4 N_DIV [4] 0 ...
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CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET Table-2 REGISTER 1 /BIT 6 REGISTER 9/BIT6 L_MODE Table-3 CPU, AGP, PCI divider ratio selection Table DS2~DS0 000 001 010 011 100 101 110 111 7.10 Register 10: Control ...
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CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET 7.11 Register 11: Control (Default: E7h) BIT NAME PWD 7 CPUT_DRI 1 CPUT output state in during POWER DOWN or Stop mode assertion. 0: Driven CPUC always tri-state (floating) in power down Assertion. ...
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CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET 7.13 Register 13: Control (Default: 24h) BIT NAME PWD 7 INV_AGP 0 6 INV_PCI 0 5 CSKEW [ CSKEW [ CSKEW [ PSKEW [ PSKEW ...
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CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET 7.16 Register 16: DRAM Buffer Control (1 = Enable Disable) (Default: 7Fh) BIT NAME PWD 7 Reserve 0 6 FBOUT_EN 1 5 DDR5 1 4 DDR4 1 3 DDR3 1 2 ...
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... MAS_VER_ID [ SUB_VER_ID [ SUB_VER_ID [0] 0 M_DIVIDER OR N_DIVIDER TIMING COUNTER FUNCTION DESCRIPTION Winbond Chip ID. W83195BR-341 (SA5861). Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. FUNCTION DESCRIPTION MASK definition for master body *A****: 01, *B****: 10, *C****: 11, *D****:00 MASK definition for code body ...
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... CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET 8. ACCESS INTERFACE 2 The W83195BR-341 provides I W83195BR-341 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I address is defined at 0xD2. Block Read and Block Write Protocol 8.1 Block Write protocol 8.2 Block Read protocol ## In block mode, the command code must filled 00H 8 ...
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CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET 9. SPECIFICATIONS 9.1 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than ...
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CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET 9.4 CPU 0.7V Electrical Characteristics ± VDDCPU= 3. IREF=2.32mA, Ioh=6*IREF PARAMETER Rise Time Fall Time Absolute crossing point Voltages Cycle to Cycle jitter Duty Cycle 9.5 CPU 1.0V ...
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CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET 9.7 PCI Electrical Characteristics ± ° VDDPCI= 3. PARAMETER Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min ...
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... W83195BR-341 28051234 342G AASA W83195BG-341 28051234 342GAASA 1st line: Winbond logo and the type number: W83195BR-341/W83195BG-341 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 342 342: packages made in '2003, week 42 G: assembly house ID ...
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CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET 12. PACKAGE DRAWING AND DIMENSIONS .035 .045 0.40/0.50 DIA E TOP VIEW SEATING PLANE e PARTING LINE b SIDE VIEW c θ DETAIL"A" Please note that all data and ...
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CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal ...