W83195BR-341-TR Nuvoton Technology Corporation of America, W83195BR-341-TR Datasheet - Page 12

• Manufacturer Part Number: W83195BR-341-TR
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83195BR-341-TR

• Lead Free Status / RoHS Status: Not Compliant

7.
(The register No. Is increased by 1 if use byte data read/write protocol)
7.1
7.2
BIT
7
6
5
4
3
2
1
0
I2C CONTROL AND STATUS REGISTERS
Register 0: Frequency Select (Default =08h)
Register 1: SRC/CPU Clock (1 = Enable, 0 = Disable) (Default: A1h)
BIT
7
6
5
4
3
2
1
0
EN_SSEL
Reserved
SPSPEN
SSEL [4]
SSEL [3]
SSEL [2]
SSEL [1]
SSEL [0]
NAME
CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET
PWD
CPUCS_C
CPUCS_T
L_MODE
CPUT/C
0
0
0
0
1
0
0
0
NAME
FS4
FS3
FS2
FS1
FS0
Software frequency table selection through I
Enable software table selection FS [4:0].
0 = Hardware table setting (Jump mode).
1 = Software table setting through Bit7~3. (Jump less mode)
Enable spread spectrum mode under clock output.
0 = Spread Spectrum mode disable
1 = Spread Spectrum mode enable
Reserved
- 8 -
PWD
FUNCTION DESCRIPTION
1
0
1
X
X
X
X
0
Pin 48,49 CPUCS_T/C output control
Selection for Pin 26. Power Down
Input / System Reset Control Output
1: System Reset feature
0: Power Down feature (Default)
Pin 53,52 CPUT/C output control
Mapping software table.
Power on latched value of FS3 (20)
pin. Default 0 (Read only)
Power on latched value of FS2 (21)
pin. Default 0 (Read only)
Power on latched value of FS1 (10)
pin. Default 0 (Read only)
Power on latched value of FS (1) pin.
Default 1 (Read only)
FUNCTION DESCRIPTION
2
C