AD9430-LVDS/PCBZ Analog Devices Inc, AD9430-LVDS/PCBZ Datasheet - Page 11

• Manufacturer Part Number: AD9430-LVDS/PCBZ
• Manufacturer: Analog Devices Inc

Specifications of AD9430-LVDS/PCBZ

• Lead Free Status / RoHS Status: Compliant

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 7. CMOS Mode Pin Function Descriptions
Pin Number
1
2, 7, 42, 43, 65, 66, 68
3
4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 35, 38, 41, 86,
87, 91, 92, 93, 96, 97, 100
5
6
8, 14, 15, 18, 19, 24, 27, 28, 29, 34, 39, 40, 88, 89, 90, 94,
95, 98, 99
10
11
21
22
32
33
36
37
44
45
SENSE
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
VREF
DNC
DNC
VIN+
VIN–
S5
S4
S2
S1
10
12
13
14
18
19
11
15
16
17
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
Figure 4. CMOS Dual-Mode Pin Configuration
Mnemonic
S5
DNC
S4
AGND
S2
S1
AVDD
SENSE
VREF
VIN+
VIN–
DS+
DS–
CLK+
CLK–
DB0
DB1
Rev. D | Page 11 of 44
2
CMOS PINOUT
(Not to Scale)
1
AD9430
TOP VIEW
Description
Full-Scale Adjust Pin. AVDD sets f
GND sets f
Do Not Connect.
Interleaved, Parallel Select Pin. High = interleaved.
Analog Ground.
Output Mode Select. Low = dual-port CMOS, high = LVDS.
Data Format Select. Low = binary, high = twos complement for
both CMOS and LVDS modes.
3.3 V Analog Supply.
Reference Mode Select Pin. Float for internal reference operation.
1.235 V Reference I/O—Function Dependent on SENSE.
Analog Input—True.
Analog Input—Complement.
Data Sync (Input)—True. Tie low if not used.
Data Sync (Input)—Complement. Tie high if not used.
Clock Input—True.
Clock Input—Complement.
B Port Output Data Bit (LSB).
B Port Output Data Bit.
S
= 1.536 V p-p differential.
69 DA0
75 DRVDD
74 DRGND
73 DA4
72 DA3
71 DA2
70 DA1
68 DNC
66 DNC
65 DNC
64 DCO+
63 DCO–
62 DRVDD
61 DRGND
60 OR_B
59 DB11
58 DB10
57 DB9
56 DB8
55
54
53
52
51
67 DRGND
S
DB7
DRVDD
DRGND
DB6
DB5
= 0.768 V p-p differential,
AD9430