AD9430-LVDS/PCBZ Analog Devices Inc, AD9430-LVDS/PCBZ Datasheet - Page 25

• Manufacturer Part Number: AD9430-LVDS/PCBZ
• Manufacturer: Analog Devices Inc

Specifications of AD9430-LVDS/PCBZ

• Lead Free Status / RoHS Status: Compliant

APPLICATION NOTES
THEORY OF OPERATION
The AD9430 architecture is optimized for high speed and ease
of use. The analog inputs drive an integrated high bandwidth
track-and-hold circuit that samples the signal prior to
quantization by the 12-bit core. For ease of use, the part
includes an on-board reference and input logic that accepts
TTL, CMOS, or LVPECL levels. The digital output logic levels
are user selectable as standard 3 V CMOS or LVDS (ANSI-644
compatible) via Pin S2.
ENCODE INPUT
Any high speed ADC is extremely sensitive to the quality of the
sampling clock provided by the user. A track-and-hold circuit is
essentially a mixer, and any noise, distortion, or timing jitter on
the clock is combined with the desired signal at the A/D output.
For that reason, considerable care has been taken in the design
of the clock inputs of the AD9430, and the user is advised to
give careful thought to the clock source.
The AD9430 has an internal clock duty cycle stabilization
circuit that locks to the rising edge of CLK+ and optimizes
timing internally. This allows for a wide range of input duty
cycles at the input without degrading performance. Jitter in
the rising edge of the input is still of paramount concern and
is not reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
30 MHz nominally. The loop has a time constant associated
Table 9. Output Select Coding
S1
(Data Format Select)
1
0
X
X
X
X
X
1
2
3
X = don’t care.
S4 used in CMOS mode only (S2 = 0). S1 to S5 all have 30 kΩ resistive pull-downs on chip.
S5 full-scale adjust (see the Analog Input section).
1
INTERLEA VED MODE
S2
(LVDS/CMOS Mode Select)
X
X
0
0
1
X
X
1
2
Rev. D | Page 25 of 44
S4
(I/P Select)
X
X
1
0
X
X
X
Figure 51.
1
PARALLEL MODE
with it that needs to be considered in applications where the
clock rate can change dynamically, requiring a wait time of
1.5 μs to 5 μs after a dynamic clock frequency increase before
valid data is available. This circuit is always on and cannot be
disabled by the user.
The clock inputs are internally biased to 1.5 V (nominal) and
support either differential or single-ended signals. For best
dynamic performance, a differential signal is recommended. An
MC100LVEL16 performs well in the circuit to drive the clock
inputs, as illustrated in Figure 50. (For trace lengths >2 inches, a
standard LVPECL termination is recommended rather than the
simple pull-down as shown.) Note that for this low voltage
PECL device, the ac coupling is optional.
In interleaved mode, output data on Port A is offset from output
data changes on Port B by one-half output clock cycle, as shown
in Figure 51.
S5
(Full-Scale Select)
X
X
X
X
X
1
0
1
Figure 50. Driving Clock Inputs with LVEL16
PECL
GATE
510Ω
3
Mode
Twos complement
Offset binary
Dual-mode CMOS interleaved
Dual-mode CMOS parallel
LVDS mode
Full scale = 0.768 V
Full scale = 1.536 V
510Ω
0.1μF
0.1μF
CLK+
CLK–
AD9430
AD9430