XC5VSX50T-1FF665C Xilinx Inc, XC5VSX50T-1FF665C Datasheet - Page 192

• Manufacturer Part Number: XC5VSX50T-1FF665C
• Description: FPGA Virtex®-5 Family 52224 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-1FF665C

• Package: 665FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 52224
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 360
• Ram Bits: 4866048
• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Chapter 5: Configurable Logic Blocks (CLBs)
192
Figure 5-17
single LUT.
X-Ref Target - Figure 5-17
As mentioned earlier, an additional output (MC31) and a dedicated connection between
shift registers allows connecting the last bit of one shift register to the first bit of the next,
without using the LUT O6 output. Longer shift registers can be built with dynamic access
to any bit in the chain. The shift register chaining and the F7AMUX, F7BMUX, and F8MUX
multiplexers allow up to a 128-bit shift register with addressable access to be implemented
in one SLICEM.
configurations that can occupy one SLICEM.
X-Ref Target - Figure 5-18
SHIFTIN (D)
A[5:0]
CLK
WE
shows two 16-bit shift registers. The example shown can be implemented in a
Figure 5-18
Figure 5-17: Dual 16-bit Shift Register Configuration
SHIFTIN1 (AX)
SHIFTIN2 (AI)
Figure 5-18: 64-bit Shift Register Configuration
(WE/CE)
(CLK)
A[3:0]
CLK
www.xilinx.com
CE
through
5
5
DI1
A[6:2]
CLK
WE
DI1
A[6:2]
CLK
WE
Figure 5-20
SRL32
SRL32
MC31
MC31
O6
O6
4
4
DI1
A[5:2]
CLK
WE
DI2
A[5:2]
CLK
WE
illustrate various example shift register
F7AMUX
SRL16
SRL16
A5 (AX)
MC31
SHIFTOUT (Q63)
O5
O6
UG190_5_17_050506
Virtex-5 FPGA User Guide
D Q
UG190 (v5.3) May 17, 2010
(MC31)
(Optional)
(AQ)
UG190_5_18_050506
Output (Q)
Registered
Output