XC5VSX50T-1FF665C Xilinx Inc, XC5VSX50T-1FF665C Datasheet - Page 246

• Manufacturer Part Number: XC5VSX50T-1FF665C
• Description: FPGA Virtex®-5 Family 52224 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-1FF665C

• Package: 665FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 52224
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 360
• Ram Bits: 4866048
• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Chapter 6: SelectIO Resources
246
HSLVDCI (High-Speed Low Voltage Digitally Controlled Impedance)
The HSLVDCI standard is intended for bidirectional use. The driver is identical to LVDCI,
while the input is identical to HSTL and SSTL. By using a V
HSLVDCI allows greater input sensitivity at the receiver than when using a single-ended
LVCMOS-type receiver.
A sample circuit illustrating bidirectional termination techniques for an HSLVDCI
controlled impedance driver is shown in
controlled impedance driver with a V
HSLVDCI_18, HSLVDCI_25, and HSLVDCI_33.
X-Ref Target - Figure 6-35
For output DC voltage specifications, refer to the LVDCI V
LVCMOS, LVDCI, and LVDCI_DV2 DC Voltage Specifications at Various Voltage
References.
Valid values of V
noise margin in specific use conditions.
Table 6-10: HSLVDCI Input DC Voltage Specifications
Figure 6-35: HSLVDCI Controlled Impedance Driver with Bidirectional Termination
V
V
V
REF
IH
IL
R 0 = R VRN = R VRP = Z 0
Standard
HSLVDCI
Table 6-10
CCO
are 1.5V, 1.8V, 2.5V, and 3.3V. Select V
lists the input DC voltage specifications when using HSLVDCI.
www.xilinx.com
IOB
V
REF
Min
–
–
+ 0.1
REF
Figure
Z 0
referenced input are: HSLVDCI_15,
6-35. The DCI I/O standards supporting a
V
CCO
IOB
Typ
–
–
/2
OH
REF
REF
V
and V
REF
to provide the optimum
-referenced input,
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
= V
R 0 = R VRN = R VRP = Z 0
OL
CCO
entries in
/2
V
REF
HSLVDCI
Max
ug190_6_33_022806
+
–
–
–
– 0.1
Table 6-9