XC5VSX50T-1FF665C Xilinx Inc, XC5VSX50T-1FF665C Datasheet - Page 284

• Manufacturer Part Number: XC5VSX50T-1FF665C
• Description: FPGA Virtex®-5 Family 52224 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-1FF665C

• Package: 665FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 52224
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 360
• Ram Bits: 4866048
• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Chapter 6: SelectIO Resources
X-Ref Target - Figure 6-76
284
DCI
SSTL2_II_T_DCI (2.5V) Split-Thevenin Termination
SSTL2_II_T_DCI
R 0 = 25
Ω
Figure 6-76: SSTL2_II_T_DCI (2.5V) Split-Thevenin Termination
Figure 6-76
SSTL2_II_T_DCI (2.5V) with on-chip split-Thevenin termination. In this bidirectional I/O
standard, when 3-stated, the termination is invoked on the receiver and not on the driver.
V
Not 3-stated
REF
= 1.25V
IOB
shows a sample circuit illustrating a valid termination technique for
Z 0
www.xilinx.com
3-stated
IOB
V
CCO
2R
2R
= 2.5V
VRP
VRN
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
V
REF
= 1.25V
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
SSTL2_II_T_DCI
ug190_6_92_041206
R 0 = 25
+
–
Ω