DK-S6-CONN-G Xilinx Inc, DK-S6-CONN-G Datasheet - Page 2

• Manufacturer Part Number: DK-S6-CONN-G
• Description: KIT, DEV, CONNECTIVITY, SPARTAN-6
• Manufacturer: Xilinx Inc

Specifications of DK-S6-CONN-G

• Kit Contents: Board, 2x USB Cables, Ethernet Cable, 4x SMA Cables, DVI-VGA Adapter
• Features: PCI Express X1 Edge Connector, SFP Transceiver Connector, Onboard JTAG Configuration Circuitry
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DOMAIN-SPECIFIC PLATFORMS
Silicon
High-Performance Connectivity Solutions for
Virtex-6 FPGAs
Low-Cost, Easy-to-Use Connectivity Solutions for
Spartan-6 FPGAs
Built-In Blocks and IP Portfolio
Support for Industry Standard AXI4™ Interface
The Xilinx Connectivity Targeted Design platforms now support the industry standard AXI interface for design creation and system integration.
Users can now use a single interface specification that can be used to target the FPGA architectures to create high performance designs and
simplify development & enhancement of these systems that include external memory and connectivity processing blocks.
Tools and Design Flows Tailored for Connectivity Designs
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Virtex-6 LXT/SXT FPGAs serve applications that require
high-performance logic, DSP, and serial connectivity, with up to
36 low-power GTX 6.5Gb/s serial transceivers
Virtex-6 HXT FPGAs are optimized for communication, switching,
and imaging systems that require the highest-speed serial
connectivity, with up to 24 GTH 1 1.18Gb/s serial transceivers and
48 GTX 6.5Gb/s serial transceivers
1.4Gb/s SelectIO™ technology to build high-bandwidth
parallel interfaces
Spartan-6 LXT FPGAs are the first to provide the necessary logic
capacity, performance, power consumption, and price points to
enable mainstream designers to use FPGA-based serial
technology with up to 8 GTP 3.125Gb/s transceivers
1.05Gb/s SelectIO technology to meet 3.3V to 1.2V parallel I/O
standards and protocols along with hot swap compliance
Maximize scalability of Virtex-6 FPGAs supporting up to 4 PCIe blocks (x1-x8 Gen1/Gen2) Endpoint and Root port configuration, up to 4
Ethernet blocks supporting 10/100/1000Mb/s operation through multiple interfaces
Simplified and optimized connectivity for Spartan-6 FPGAs using 1 PCIe block (x1 Gen1) Endpoint configuration and 4 Memory Interface
controller blocks supporting DDR, DDR2, DDR3, and LP DDR interfaces
Xilinx IP portfolio, available through the CORE Generator™ system enables design with multiple protocols, streamlines design process, and
improves design quality
Alliance Partner IP portfolio simplifies and maximizes design flexibility and reduces risk by supporting additional serial/parallel protocols and
hardware acceleration functions
Front-to-back design methodology with ISE Design Suite Logic/Embedded editions
Architecture Wizards–Transceiver, Clocking, CRC Wizards
Design analysis and synthesis–PlanAhead™ (floorplanning and PinLayout) and XST
Implementation tool–MAP, Timing driven Place & Route (P&R), and SmartXplorer
Debug tools–ChipScope™ Pro, SerialIO ToolKit, FPGA Editor
Guidelines and reports:
- Signal integrity considerations
- Transceiver characterization: generic and protocol specific reports
- PCB design guidelines
VIRTEX 6 LXT FPGA
VIRTEX 6 SXT FPGA
VIRTEX 6 HXT FPGA
SPARTAN 6 LX FPGA
SPARTAN 6 LXT FPGA
• High Logic Density
• High-Speed Serial Connectivity
• Lowest-Cost Logic
• Lowest-Cost Logic
• Low-Cost Serial Connectivity
- 36 Low-Power GTX 6.5Gb/s Transceivers
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8 GTP 3.1258Gb/s Transcievers
• High Logic Density
• High-Speed Serial Connectivity
• Enhanced DSP
- 36 Low-Power GTX 6.5Gb/s Transceivers
• High Logic Density
• Ultra High-Speed Serial Connectivity
- 24 GTH 11.18Gb/s Transcievers and
48 GTX 6.5Gb/s Transceivers
ConneCtivity
LOGIC
BLOCK RAM
DSP
PARALLEL I/O
SERIAL I/O
LOGIC
BLOCK RAM
DSP
PARALLEL I/O
SERIAL I/O