DK-S6-CONN-G Xilinx Inc, DK-S6-CONN-G Datasheet - Page 3

• Manufacturer Part Number: DK-S6-CONN-G
• Description: KIT, DEV, CONNECTIVITY, SPARTAN-6
• Manufacturer: Xilinx Inc

Specifications of DK-S6-CONN-G

• Kit Contents: Board, 2x USB Cables, Ethernet Cable, 4x SMA Cables, DVI-VGA Adapter
• Features: PCI Express X1 Edge Connector, SFP Transceiver Connector, Onboard JTAG Configuration Circuitry
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Glue
Logic
DOMAIN-SPECIFIC PLATFORMS
Targeted Reference Designs
Accelerate system design development by integrating critical components–transceivers, IP blocks, and memory controllers. The connectivity kit
framework includes:
Virtex-6 Connectivity Targeted Reference Design includes:
C O N N ECTIVITY K IT D ES I G N F LOW
PCIe Gen2
PCIe Gen1
(2.5 Gbps)
(5.0Gbps)
•
•
•
•
•
•
•
•
•
•
•
X4
OR
X8
Complete end-to-end system design enabling building block FPGA design architecture
Design fully tested, validated, supported, maintained, and updated for every revision of the ISE software release
Hardware Design Elements: RTL and IP files simulation environment, implementation scripts, and FPGA programming files
Enabling System Design using the industry standard AXI4 Streaming, Memory Mapped, Lite Interfaces for interfacing different IP blocks
Software Design Elements: source files including–device drivers, APIs, application, and GUI
Demonstration and documentation: User Guides, Getting Started Guides, Hardware Setup Guides
GTX transceivers running at PCIe (5.0Gb/s) and XAUI
(3.125Gb/s) line rates
Xilinx IP LogiCORE for PCI Express Endpoint-x4 Gen2
or x8 Gen1
Northwest Logic Packet DMA supporting >20G
aggregate bandwidth
Xilinx Virtual-FIFO memory controller design
Xilinx IP LogiCORE for XAUI
Memory
1. GETTING STARTED
• Read the Getting Started Guide
• Connect the cables
• Power-up the board
• Load the reference designs
• Demo up and running
LogiCore IP
PCI Express
Non-
Xilinx
for
Mixed
Signal
PCIe Packet DMA
Virtex-6 LXT FPGA
Embedded
Logic
User Application
Packet DMA
IP
& Memory
Controller
Interface
Controller
Memory
User Application
LogiCORE
XAUI
IP
• Evaluate reference design
using interactive web-based
user interface
2. EVALUATE
(3.125Gbps)
SODIMM
DDR3
XAUI
Glue
Logic
Spartan-6 Connectivity Targeted Reference Design includes:
•
•
•
•
•
(2.5Gbps)
Memory
GTP transceivers running at PCIe (2.5Gb/s) and GbE (1.25Gb/s)
line rates
Xilinx IP LogiCORE for PCI Express Endpoint–x1 Gen1
Northwest Logic Packet DMA supporting >3G
aggregate bandwidth
Xilinx Virtual-FIFO memory controller design using built-in
Memory Interface Controller Block
Xilinx IP LogiCORE for Ethernet supporting GMII and SFP
interfaces
PCIe
Gen1
x1
Non-
Xilinx
LogiCore IP
PCI Express
for
Mixed
Signal
PCIe Packet DMA
• Open the design tools
• Customize the reference designs
• Generate a new design
• Download and run
Embedded
Logic
Spartan-6 LXT FPGA
3. CUSTOMIZE
User Application
IP
Local Link to
Local Link to
AXI4-Stream
Interface
Interface
AXI4-Lite
AXI4
Ethernet
ConneCtivity
AXI
MIG
AXI
GTP
GbE (SFP)
GbE (RJ-45)
Component
DDR3