LU82551IT S L7G3 Intel, LU82551IT S L7G3 Datasheet - Page 75
LU82551IT S L7G3
Manufacturer Part Number
LU82551IT S L7G3
Description
Manufacturer
Intel
Datasheet
1.LU82551IT_S_L7G3.pdf
(102 pages)
Specifications of LU82551IT S L7G3
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
196
Lead Free Status / RoHS Status
Compliant
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9.3.13
9.3.14
Datasheet
Table 43. Register 28: MDI/MDI-X Control
Table 44. Register 29: Hardware Integrity Control
Register 28: MDI/MDI-X Control Register
Register 29: Hardware Integrity Control Register
15
14
13
Bit(s)
Bit(s)
15:8
3:0
7
6
5
4
HWI Enable
Ability Check
Test Execute
Reserved
Auto Switch
Enable
Switch
Status
Auto Switch
Complete
Resolution Timer
Name
Name
to enter HWI test mode.
1 = HWI enabled
0 = HWI disabled
This bit reports the results of the HWI ability check
and is valid 100 µs after the HWI Enabled bit (bit 15 of
this register) is set (1b).
1 = Test passed
0 = Test failed (HWI ability not detected)
When this bit is set, the PHY unit launches test pulses
on the wire to determine the distance to the cable’s
high or low impedance point.
1 = Execute test
0 = Do not execute test
Reserved for future use. Set these bits to 0.
Enables the MDI/MDI-X feature (writing to this bit
overwrites the default value).
1 = Enabled.
0 = Disabled.
Manual switch (valid only if bit 7 is set to 0).
1 = Forces the port to be MDI-X (cross-over).
0 = Forces the port to be MDI (straight-through)
Indicates the state of the MDI pair.
1 = MDI-X (cross-over).
0 = MDI (straight-through).
Indicates when the correct configuration is achieved.
1 = Resolution algorithm has completed.
0 = Resolution algorithm has not completed.
Defines the minimum slot time the algorithm uses in
order to switch between one configuration or another.
0000 = 80ms.
1111 = 105ms.
This bit enables the HWI feature causing the PHY unit
Description
Definition
Networking Silicon — 82551IT
0
0
0
0
1
0000
Default
Default
0
R/W
R/W
R/W
RO
RO
R/W
RW
RO
WO
R/W
R/W
69
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