LE58QL02FJC Zarlink, LE58QL02FJC Datasheet - Page 33

• Manufacturer Part Number: LE58QL02FJC
• Description: SLIC 4-CH 3.3V 44-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of LE58QL02FJC

• Package: 44PLCC
• Number Of Channels Per Chip: 4
• Minimum Operating Supply Voltage: 3.135 V
• Typical Operating Supply Voltage: 3.3 V

SIGNAL PROCESSING
Overview of Digital Filters
Several of the blocks in the signal processing section are user programmable. These allow the user to optimize the performance
of the QLSLAC device for the system. Figure 24 shows the QLSLAC device signal processing and indicates the programmable
blocks.
The advantages of digital filters are:
Two-Wire Impedance Matching
Two feedback paths on the QLSLAC device synthesize the two-wire input impedance of the SLIC device by providing a
programmable feedback path from VIN to VOUT. The Analog Impedance Scaling Network (AISN) is a programmable analog gain
of −0.9375 • GIN to +0.9375 • GIN from V
programmable digital filter providing an additional path and programming flexibility over the AISN in modifying the transfer
function from VIN to VOUT. Together, the AISN and the Z-Filter enable the user to synthesize virtually all required SLIC device
input impedances.
Frequency Response Correction and Equalization
The QLSLAC device contains programmable filters in the receive (R) and transmit (X) directions that may be programmed for
line equalization and to correct any attenuation distortion caused by the Z filter.
Transhybrid Balancing
The QLSLAC device’s programmable B filter is used to adjust transhybrid balance. The filter has a single pole IIR section (BIIR)
and an eight-tap FIR section (BFIR), both operating at 16 kHz. (See commands 86/87h and 96/97h.)
High reliability
No drift with time or temperature
Unit-to-unit repeatability
Superior transmission performance
Flexibility
Maximum possible bandwidth for V.90 modems
V
IN
GIN
V
Full
Digital
Loopback
(FDL)
OUT
AISN
+
VREF
*
AX
*
AR
Figure 24. QLSLAC Device Transmission Block Diagram
*
ADC
DAC
* programmable blocks
polator
mator
Deci-
Inter-
IN
to V
+
Zarlink Semiconductor Inc.
Z
OUT
. (See GIN in
*
polator
High Pass Filter (HPF)
mator
Deci-
Inter-
33
+
B
Electrical Characteristics, on page
*
GR
GX
*
*
Lower Receive
Gain (LRG)
X
R
*
*
LPF &
HPF
LPF
TSA Loopback
Cutoff Receive
0
Path (CRP)
pressor
(TLB)
pander
Com-
Ex-
1 kHz Tone
(TON)
13.) The Z filter is a
TSA
TSA
Cutoff
Transmit
Path
(CTP)
Digital
RX
Digital
TX