SI5315B-C-GMR Silicon Laboratories Inc, SI5315B-C-GMR Datasheet - Page 17

• Manufacturer Part Number: SI5315B-C-GMR
• Description: IC CLOCK MULT 8KHZ-125MHZ 36QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5315B-C-GMR

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 36-VQFN
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5315
3.2. PLL Performance
The Si5315 provides extremely low jitter generation, a well-controlled jitter transfer function, and high jitter
tolerance due to the high level of integration.
3.2.1. Jitter Generation
Jitter generation is defined as the amount of jitter produced at the output of the device with a jitter free input clock.
Generated jitter arises from sources within the VCO and other PLL components. Jitter generation is a function of
the PLL bandwidth setting. Higher loop bandwidth settings may result in lower jitter generation, but may result in
less attenuation of jitter that might be present on the input clock signal.
3.2.2. Jitter Transfer
Jitter transfer is defined as the ratio of output signal jitter to input signal jitter for a specified jitter frequency. The
jitter transfer characteristic determines the amount of input clock jitter that passes to the outputs. The DSPLL
technology used in the Si5315 provides tightly controlled jitter transfer curves because the PLL gain parameters
are determined largely by digital circuits which do not vary over supply voltage, process, and temperature. In a
system application, a well-controlled transfer curve minimizes the output clock jitter variation from board to board
and provides more consistent system level jitter performance.
The jitter transfer characteristic is a function of the loop bandwidth setting. Lower bandwidth settings result in more
jitter attenuation of the incoming clock, but may result in higher jitter generation. Figure 7 shows the jitter transfer
curve mask.
Jitter
Transfer
Jitter Out
Jitter In
0 dB
Peaking
–20 dB/dec.
f
BW
Jitter
Figure 7. PLL Jitter Transfer Mask/Template
Rev. 0.26
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