W134SH Cypress Semiconductor Corp, W134SH Datasheet - Page 5

• Manufacturer Part Number: W134SH
• Description: IC CLK GEN DIR RAMBUS 3.3V24QSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Direct RAMbus Clock Generatorr

Specifications of W134SH

• Output: RSL
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-QSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Input: -
• Other names: 428-1475

Document #: 38-07426 Rev. *B
Table 4. Bypass and Test Mode Selection
Table 5 shows the logic for selecting the Power-down mode,
using the PwrDnB input signal. PwrDnB is active LOW
(enabled when 0). When PwrDnB is disabled, the DRCG is in
its normal mode. When PwrDnB is enabled, the DRCG is put
into a powered-off state, and the Clk and ClkB outputs are
three-stated.
Table 5. Power-down Mode Selection
Table 6. Examples of Frequencies, Dividers, and Gear Ratios
The control signals Mult0 and Mult1 can be used in two ways.
If they are changed during Power-down mode, then the
Power-down transition timings determine the settling time of
the DRCG. However, the Mult0 and Mult1 control signals can
also be changed during Normal mode. When the Mult control
signals are “hot-swapped” in this manner, the Mult transition
timings determine the settling time of the DRCG.
In Normal mode, the clock source is on, and the output is
enabled.
Table 7 lists the control signals for each state.
Normal
Output Test (OE)
Bypass
Test
Power-down
Normal
Mode
Pclk
100
100
133
133
Mode
67
PwrDnB
Refclk
S0
1
0
0
0
1
1
33
50
50
67
67
S1
0
1
0
1
VDD Turn-On
Bypclk
PLLclk
Refclk
Busclk
(int.)
Gnd
PAclk
GND
267
300
400
267
400
Clk
–
VDD Turn-On
Test
M
K
PLLclk PLLclkB
Refclk
PAclk
Hi-Z
Power-Down
Clk
Figure 4. Clock Source State Diagram
Synclk
PAclkB
100
100
N
67
75
67
ClkB
GND
L
RefclkB
B
PAclkB
ClkB
Hi-Z
A
VDD Turn-On
Normal
A
8
6
8
4
6
Table of Frequencies and Gear Ratios
Table 6
frequencies, the corresponding A and B dividers required in
the DRCG PLL, and the corresponding M and N dividers in the
gear ratio logic. The column Ratio gives the Gear Ratio as
defined Pclk/Synclk (same as M and N). The column F@PD
gives the divided down frequency (in MHz) at the Phase
Detector, where F@PD = Pclk/M = Synclk/N.
State Transitions
The clock source has three fundamental operating states.
Figure 4 shows the state diagram with each transition labelled
A through H. Note that the clock source output may NOT be
glitch-free during state transitions.
Upon powering up the device, the device can enter any state,
depending on the settings of the control signals, PwrDnB and
StopB.
In Power-down mode, the clock source is powered down with
the control signal, PwrDnB, equal to 0. The control signals S0
and S1 must be stable before power is applied to the device,
and can only be changed in Power-down mode (PwrDnB = 0).
The reference inputs, V
be grounded during the Power-down mode.
Table 7. Control Signals for Clock Source States
Figure 5 shows the timing diagrams for the various transitions
between states, and Table 8 specifies the latencies of each
state transition. Note that these transition latencies assume
the following.
Refclk input has settled and meets specification shown in
Table .
Mult0, Mult1, S0 and S1 control signals are stable.
Power-down
Clock Stop
Normal
G
D
C
State
E
B
shows
1
1
1
1
1
J
Clk Stop
F
PwrDnB
several
0
1
1
M
2
8
4
4
8
DDR
and V
supported
VDD Turn-On
StopB
H
X
0
1
N
2
6
4
2
6
DDPD
W134M/W134S
, may remain on or may
Source
Clock
OFF
Pclk
Ratio
ON
ON
1.33
1.33
1.0
1.0
2.0
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and
Disabled
Enabled
Ground
Output
Buffer
F@PD
12.5
16.7
33
25
33
Busclk