BBT3821-JH Intersil, BBT3821-JH Datasheet - Page 37

• Manufacturer Part Number: BBT3821-JH
• Description: IC RE-TIMER OCTAL 192-BGA
• Manufacturer: Intersil
• Type: Clock and Data Recovery (CDR)r

Specifications of BBT3821-JH

• Input: Differential
• Output: CML
• Frequency - Max: 3.1875GHz
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 192-EBGA
• Frequency-max: 3.1875GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (2): If ‘Indirect DOM Enable’ is set, then the DOM A/D and Flag values are loaded from the I
(Approximate, based on REF_CLOCK = 156.25 MHz; default underlined)
Note (1): See Table 38 and Table 51 for these registers.
Note (2): These are the Default values. The value in 1.C018’h may be overwritten by the Auto-Configure operation
Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
1.49176.15:6
1.49176.5
1.49176.4:3
1.49176.2
1.49176.1:0
00
01
10
11
1.49177.15:8
1.49177.7:0
1.49178.15:8
1.49178.7:0
1.49179.15:9
1.49179.8
1.49179.7:1
1.49179.0
1.49180.15:8
1.49180.7
1.49180.7:1
1.49180.0
(2)
(1.A100’h.1:0) BITS
Table 54, and ‘Representative’ controls which lane’s A/D values will appear in 1.A060:D’h. If not, then ‘Representative’ has no effect, and the full DOM area is
updated from a single DOM device. See “DOM Registers” on page 16 for details.
BIT
BIT
BIT
1.41216.1:0
Reserved
Test Control
DOM Update period
Indirect DOM Enable
Representative
Lane 3 DOM
Lane 2 DOM
Lane 1 DOM
Lane 0 DOM
Lane 3 DOM
Not used, Set by current operation
Lane 2 DOM
Not used, Set by current operation
Lane 1 DOM
Not used, Set by current operation
Lane 0 DOM
Not used, Set by current operation
(1)
NAME
NAME
NAME
37
N/A
800ms
400ms
100ms
Table 54. DOM INDIRECT MODE DEVICE ADDRESS REGISTERS
Table 53. DOM INDIRECT MODE START ADDRESS REGISTERS
Table 52. DOM PERIODIC UPDATE WAITING TIME VALUES
MDIO REGISTER ADDRESSES = 1.49179:80 (1.C01B:1C’h)
MDIO REGISTER ADDRESSES = 1.49177:8 (1.C019:1A’h)
(2)
00
MDIO REGISTER ADDRESS = 1.49176 (1.C018’h)
See Table 52
1 = Enable
0 = Disable
Lane value
Start Address
Start Address
Start Address
Start Address
Device Address
Device Address
Device Address
Device Address
(2)
Table 51. DOM CONTROL REGISTER
SETTING
SETTING
SETTING
N/A
1000ms
500ms
150ms
BBT3821
0’b
00’h
0’b
00’b
60’h
60’h
60’h
60’h
DEFAULT
DEFAULT
54’h
53’h
52’h
51’h
01
DEFAULT
(2)
1.49176.4:3 (1.C018’h) BITS
(2)
(1)
(1)
(1)
2
C spaces pointed to by the Indirect Mode values in Table 53 and
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
N/A
1300ms
600ms
200ms
R/W
R/W
R/W
Controls rates at which DOM A/D values are
Start address to read A/D values
User must keep at 0.
updated
Enable updates from four DOM devices. See
Table 33, Table 38
Select Lane for 1.A060:D’h
from DOM monitor device of respective lane
Note: I
from DOM monitor device of respective lane is
twice set value. Thus ‘Default’ column
addresses are A8’h, A6’h A4’h and A2’h for
Lanes 3, 2, 1 & 0 respectively. LSB reflects
‘Read’ operation value
10
(1)
2
C Device address to read A/D values
DESCRIPTION
DESCRIPTION
DESCRIPTION
N/A
1600ms
700ms
300ms
11