BBT3821-JH Intersil, BBT3821-JH Datasheet - Page 38

• Manufacturer Part Number: BBT3821-JH
• Description: IC RE-TIMER OCTAL 192-BGA
• Manufacturer: Intersil
• Type: Clock and Data Recovery (CDR)r

Specifications of BBT3821-JH

• Input: Differential
• Output: CML
• Frequency - Max: 3.1875GHz
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 192-EBGA
• Frequency-max: 3.1875GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (1): ‘V’ is a version number. See “JTAG & AC-JTAG Operations” on page 53 for a note about the version number.
Note (2): For rows with “A”, the default value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92
Note (3): Read value depends on status signal values. Value shown indicates ‘normal’ operation.
Note (4): The IEEE 802.3ae specification allows this to be all zeroes. A XENPAK (etc.) host can more readily determine where the NVR registers are if this value is zero.
Note (5): If IEEE 802.3ae (and default) setting for PCS Loopback, 180F’h. If PCS Loopback allowed, 1C0F’h. See Table 61 and Table 64.
1.49181.15:7
1.49181.6
1.49181.5
1.49181.4
1.49181.3
1.49181.2
1.49181.1
1.49181.0
3.0
3.1
3.2:3
3.4
3.5
3.6
3.7
3.8
3.14:15
3.24
3.25
3.49152
3.49153
3.49154
3.49155
3.49156
3.49159
3.49160
3.49161
3.49164
3.49165
3.49166
3.49167
DEC
ADDRESS
for details).
BIT
3.0
3.1
3.2:3
3.4
3.5
3.6
3.7
3.8
3.E:F
3.18
3.19
3.C000
3.C001
3.C002
3.C003
3.C004
3.C007
3.C008
3.C009
3.C00C
3.C00D
3.C00E
3.C00F
HEX
Reserved
OPRLOS[3:0]
TX_ENA[3:0]
TX_ENC
OPRXOP
OPTTEMP
OPTXLBC
OPTXLOP
PCS Control 1
PCS Status 1
ID Code
Speed Ability
IEEE Devices
Vendor Devices
PCS Type
PCS Status 2
Package ID
PCS-X Status 3
PCS Test
PCS Control 2
PCS Control 3
PCS ERROR
PCS IDLE
PCS // Loop Back PCS PARALLEL NETWORK LOOP BACK
Test_Flags
Output Ctrl
Half Rate
BIST Ctrl
BIST Error
Soft Reset
NAME
NAME
38
Table 55. OPTICAL STATUS & CONTROL PIN POLARITY REGISTER
Reset, Enable loop back mode.
PCS Fault, Link Status
Manufacturer and Device OUI
Devices in Package, Clause 22 capable
Vendor Specific Devices in Pkg
IEEE PCS TYPE SELECT REGISTER
Device Present, Local Fault, Type Summary
Package OUI, etc.
IEEE 10GBASE-X PCS TEST CONTROL
REGISTER
PCS CONTROL REGISTER 2
PCS Control Register 3
PCS INTERNAL ERROR CODE REGISTER
PCS INTERNAL IDLE CODE REGISTER
CONTROL REGISTER
Receive Path Test & Status Flags
Output Control and Test function
Half rate clock mode enable
BIST Control Register
BIST ERROR Counter Registers
Reset (non MDIO)
10Gbps Ability
IEEE 10GBASE-X PCS STATUS REGISTER
MDIO REGISTER ADDRESS = 1.49181 (1.C01D’h)
1 = low -> LOS
0 = high -> LOS
1 = Active Low
0 = Active Hi
1 = Pin Low to trigger
LASI
0 = Pin High to trigger
LASI
Table 56. MDIO PCS DEVAD 3 REGISTERS
SETTING
PCS DEVICE 3 MDIO REGISTERS
DESCRIPTION
BBT3821
0’b
0’b
0’b
0’b
0’b
0’b
0’b
DEFAULT
(1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2040’h
0004’h
01839C6V’h
0001’h
001A’h
0000’h
0001’h
8002’h
00000000’h
See
0000’h
0F6F’h
0801’h
00FE’h
0007’h
0000’h
0000’h
AAAA’h
0000’h
0000’h
0000’h
0000’h
Input polarity to 1.10 and enable Byte Synch in
LX4 mode
Polarity of TX_ENA outputs
Polarity of TX_ENC input
Control Polarity of respective input pins which
will trigger LASI (if enabled)
DEFAULT
(5)
(3)
(3)
AC
A
A
A
A
A
DESCRIPTION
(2)
R/W
RO LL
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
RO LH
R/W
R/W
R/W
RO/
RCNR
R/W SC
R/W
Table 57
Table 58
See
Table 7
Table 8
Table 8
Table 59
Table 60
See
Table 61
Table 62
Table 63
Table 64
Table 66
Table 67
Table 68
Table 69
Table 70
Table 71
Table 72
Table 73
Table 46
DETAILS
(1)
(4)