CY29947AXC Cypress Semiconductor Corp, CY29947AXC Datasheet - Page 2
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CY29947AXC
Manufacturer Part Number
CY29947AXC
Description
IC CLK BUFF 1:9 200MHZ 32TQFP
Manufacturer
Cypress Semiconductor Corp
Type
Fanout Buffer (Distribution), Multiplexerr
Datasheet
1.CY29947AXC.pdf
(7 pages)
Specifications of CY29947AXC
Package / Case
32-TQFP
Number Of Circuits
1
Ratio - Input:output
2:9
Differential - Input:output
Yes/No
Input
LVCMOS, LVTTL
Output
LVCMOS, LVTTL
Frequency - Max
200MHz
Voltage - Supply
2.375 V ~ 3.63 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Frequency-max
200MHz
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Multiply / Divide Factor
1:9
Number Of Clock Inputs
2
Output Logic Level
LVCMOS, LVTTL
Supply Voltage (max)
3.63 V
Supply Voltage (min)
2.375 V
Maximum Operating Temperature
+ 70 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-2235
CY29947AXC
CY29947AXC
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY29947AXC
Manufacturer:
Renesas
Quantity:
29
Company:
Part Number:
CY29947AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY29947AXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Pin Description
Note:
Output Enable/Disable
The CY29947 features a control input to enable or disable the
outputs. This data is latched on the falling edge of the input
clock. When SYNC_OE is asserted LOW, the outputs are dis-
abled in a LOW state. When SYNC_OE is set HIGH, the out-
puts are enabled as shown in Figure 1.
Document #: 38-07287 Rev. *C
1.
11, 13, 15, 19,
21, 23, 26, 28,
10, 14, 18, 22,
1, 8, 9, 12, 16,
17, 20, 24, 25,
PD = internal pull-down, PU = internal pull-up.
27, 31
29, 32
Pin
30
3
4
2
5
6
7
SYNC_OE
TCLK
Q
TCLK_SEL
SYNC_OE
[1]
TCLK0
TCLK1
Name
Q(8:0)
VDDC
VDD
VSS
TS#
VDDC
PWR
Figure 1. SYNC_OE Timing Diagram
I, PU
I, PU
I, PU
I, PU
I, PU
I/O
O
Test Clock Input
Test Clock Input
Test Clock Select Input. When LOW, TCLK0 is selected. When assert-
ed HIGH, TCLK1 is selected.
Clock Outputs
Output Enable Input. When asserted HIGH, the outputs are enabled
and when set LOW the outputs are disabled in a LOW state.
Three-state Control Input. When asserted LOW, the output buffers are
three-stated. When set HIGH, the output buffers are enabled.
3.3V or 2.5V Power Supply for Output Clock Buffers
3.3V or 2.5V Power Supply
Common Ground
Description
CY29947
Page 2 of 7
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