AD9510BCPZ Analog Devices Inc, AD9510BCPZ Datasheet - Page 46

• Manufacturer Part Number: AD9510BCPZ
• Description: IC CLOCK DIST 8OUT PLL 64LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Divider, PLLr

Specifications of AD9510BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 8
• No. Of Multipliers / Dividers: 8
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9510-VCO/PCBZ - BOARD EVALUATION FOR AD9510AD9510/PCBZ - BOARD EVALUATION FOR AD9510
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9510
REGISTER MAP AND DESCRIPTION
SUMMARY TABLE
Table 23. AD9510 Register Map
Addr
(Hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
OE-
33
34
35
36
37
38
39
Parameter
Serial
Control Port
Configuration
PLL
A Counter
B Counter
B Counter
PLL 1
PLL 2
PLL 3
PLL 4
R Divider
R Divider
PLL 5
FINE DELAY
ADJUST
Delay Bypass 5
Delay Full-
Scale 5
Delay Fine
Adjust 5
Delay Bypass 6
Delay Full-
Scale 6
Bit 7 (MSB)
(Bidirectional
SDO Inactive
Not Used
Not Used
Not Used
Not Used
Not Used
Mode)
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Bit 6
Polarity
Bypass
Enable
Digital
Lock
First
PFD
Det.
LSB
LOR Lock_Del
B
<6:5>
CP Current <6:4>
Bit 5
Window
14-Bit R Divider Bits 13:8 (MSB) <7:0>
Digital
Reset
13-Bit B Counter Bits 7:0 (LSB) <7:0>
PLL Mux Select <5:2>Signal on STATUS
Used
Lock
Soft
Det.
Not
Ramp Capacitor <5:3>
Ramp Capacitor <5:3>
Not Used
Not Used
Rev. A | Page 46 of 60
Bit 4
Instruction
Long
14-Bit R Divider Bits 13:8 (MSB) <5:0>
Not Used
Not Used
Not Used
Not Used
Not Used
5-Bit Fine Delay <5:1>
Not Used
Prescaler P <4:2>
13-Bit B Counter Bits 12:8 (MSB) <4:0>
pin
6-Bit A Counter <5:0>
Not Used
Bit 3
Used
Not
Bit 2
Counter
Reset R
Enable
LOR
Ramp Current <2:0>
Ramp Current <2:0>
Not Used
Bit 1
Counter
Reset N
Power-Down <1:0>
Pulse Width <1:0>
CP Mode <1:0>
Antibacklash
Not Used
Bit 0
(LSB)
Counters
Reset All
Must be
Bypass
Bypass
0
Def.
Value
(Hex)
10
00
00
00
00
00
00
01
00
00
00
01
00
00
04
01
00
Notes
PLL Starts
in Power-
Down
N Divider
(A)
N Divider
(B)
N Divider
(B)
N Divider
(P)
R Divider
R Divider
Fine
Delays
Bypassed
Bypass
Delay
Max.
Delay Full-
Scale
Min. Delay
Value
Bypass
Delay
Max.
Delay Full-
Scale